Lines Matching refs:t0

125 	mfc0	t0, CP0_CONFIG, 1
126 	bgez	t0, l2_probe_done
136 	mfc0	t0, CP0_CONFIG, 2
137 	bgez	t0, l2_probe_cop0
138 	mfc0	t0, CP0_CONFIG, 3
139 	bgez	t0, l2_probe_cop0
140 	mfc0	t0, CP0_CONFIG, 4
141 	bgez	t0, l2_probe_cop0
144 	mfc0	t0, CP0_CONFIG, 5
145 	and	R_L2_L2C, t0, MIPS_CONF5_L2C
151 	PTR_LI	t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
152 	lw	t1, GCR_L2_CONFIG(t0)
172 	sw	t1, GCR_L2_CONFIG(t0)
177 	sw	zero, GCR_L2_TAG_ADDR(t0)
178 	sw	zero, GCR_L2_TAG_ADDR_UPPER(t0)
179 	sw	zero, GCR_L2_TAG_STATE(t0)
180 	sw	zero, GCR_L2_TAG_STATE_UPPER(t0)
181 	sw	zero, GCR_L2_DATA(t0)
182 	sw	zero, GCR_L2_DATA_UPPER(t0)
195 	mfc0	t0, CP0_CONFIG, 2
197 	srl	R_L2_LINE, t0, MIPS_CONF2_SL_SHF
203 	srl	t1, t0, MIPS_CONF2_SA_SHF
208 	srl	t1, t0, MIPS_CONF2_SS_SHF
215 	or	t0, t0, MIPS_CONF2_L2B
216 	mtc0	t0, CP0_CONFIG, 2
218 	mfc0	t0, CP0_CONFIG, 2
219 	and	R_L2_BYPASSED, t0, MIPS_CONF2_L2B
274 	PTR_LI		t0, INDEX_BASE
275 	PTR_ADDU	t1, t0, R_L2_SIZE
276 1:	cache		INDEX_STORE_TAG_SD, 0(t0)
277 	PTR_ADDU	t0, t0, R_L2_LINE
278 	bne		t0, t1, 1b
310 	PTR_LI		t0, INDEX_BASE
311 	PTR_ADDU	t1, t0, R_IC_SIZE
313 	cache_loop	t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
316 	PTR_LI		t0, INDEX_BASE
317 	cache_loop	t0, t1, R_IC_LINE, FILL
319 	PTR_LI		t0, INDEX_BASE
320 	cache_loop	t0, t1, R_IC_LINE, INDEX_STORE_TAG_I
325 	mfc0		t0, CP0_CONFIG
328 	ins		t0, t1, 0, 3
330 	ori		t0, t0, CONF_CM_CMASK
331 	xori		t0, t0, CONF_CM_CMASK
332 	or		t0, t0, t1
334 	mtc0		t0, CP0_CONFIG
340 	PTR_LI		t0, INDEX_BASE
341 	PTR_ADDU	t1, t0, R_DC_SIZE
343 	cache_loop	t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
346 	PTR_LI		t0, INDEX_BASE
347 2:	LONG_L		zero, 0(t0)
348 	PTR_ADDU	t0, R_DC_LINE
349 	bne		t0, t1, 2b
351 	PTR_LI		t0, INDEX_BASE
352 	cache_loop	t0, t1, R_DC_LINE, INDEX_STORE_TAG_D
367 	li		t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
368 	lw		t1, GCR_L2_CONFIG(t0)
370 	sw		t1, GCR_L2_CONFIG(t0)
375 1:	mfc0		t0, CP0_CONFIG, 2
376 	xor		t0, t0, MIPS_CONF2_L2B
377 	mtc0		t0, CP0_CONFIG, 2
383 	mfc0		t0, CP0_CONFIG, 1
384 	bgez		t0, 2f
385 	mfc0		t0, CP0_CONFIG, 2
386 	bgez		t0, 2f
389 	mfc0		t0, CP0_CONFIG, 3
390 	and		t0, t0, MIPS_CONF3_CMGCR
391 	beqz		t0, 2f
394 	mfc0		t0, CP0_CONFIG
397 	ins		t0, t1, 0, 3
399 	ori		t0, t0, CONF_CM_CMASK
400 	xori		t0, t0, CONF_CM_CMASK
401 	or		t0, t0, t1
403 	mtc0		t0, CP0_CONFIG
409 	PTR_LI		t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
410 	lw		t1, GCR_REV(t0)
415 1:	sw		t3, GCR_Cx_COHERENCE(t0)
434 	mfc0	t0, CP0_CONFIG
436 	andi	t0, t0, CONF_CM_CMASK
438 	beq	t0, t1, 2f
450 	mfc0	t0, CP0_CONFIG
452 	and	t0, t0, t1
453 	ori	t0, t0, CONF_CM_UNCACHED
454 	mtc0	t0, CP0_CONFIG
465 	mfc0	t0, CP0_CONFIG
466 	ori	t0, CONF_CM_CMASK
467 	xori	t0, CONF_CM_CMASK
468 	ori	t0, CONFIG_SYS_MIPS_CACHE_MODE
469 	mtc0	t0, CP0_CONFIG