Lines Matching refs:t0
81 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
82 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
84 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
86 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
89 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
100 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
106 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
110 li t0, CKSEG1ADDR(AR933X_RTC_BASE)
112 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
118 sw t1, AR933X_RTC_REG_RESET(t0)
123 sw t1, AR933X_RTC_REG_RESET(t0)
129 lw t1, AR933X_RTC_REG_STATUS(t0)
135 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
145 sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
148 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
153 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
157 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
159 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
172 sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
186 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
189 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
197 sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
210 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
215 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
233 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
234 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
237 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
249 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
254 lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
259 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
271 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
273 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)