Lines Matching refs:t0
101 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
102 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
105 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
107 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
110 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
114 li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
116 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
122 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
127 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
129 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
130 sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
131 sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
132 sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
134 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
135 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
137 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
141 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
145 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
149 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
152 lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
155 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
158 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
161 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
164 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
167 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
171 sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
175 sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
178 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
180 sw t1, 0xb4(t0)