44 	unsigned long end, line_size;  in invalidate_icache_all()  local
46 	end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);  in invalidate_icache_all()
48 		end -= line_size;  in invalidate_icache_all()
49 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));  in invalidate_icache_all()
51 		end -= line_size;  in invalidate_icache_all()
52 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));  in invalidate_icache_all()
54 		end -= line_size;  in invalidate_icache_all()
55 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));  in invalidate_icache_all()
56 		end -= line_size;  in invalidate_icache_all()
57 		__asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));  in invalidate_icache_all()
58 	} while (end > 0);  in invalidate_icache_all()
61 void invalidate_icache_range(unsigned long start, unsigned long end)  in invalidate_icache_range()  argument
66 	while (end > start) {  in invalidate_icache_range()
117 void invalidate_icache_range(unsigned long start, unsigned long end)  in invalidate_icache_range()  argument
139 	unsigned long end, line_size;  in dcache_wbinval_all()  local
141 	end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);  in dcache_wbinval_all()
143 		end -= line_size;  in dcache_wbinval_all()
144 		__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));  in dcache_wbinval_all()
145 		__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));  in dcache_wbinval_all()
146 		end -= line_size;  in dcache_wbinval_all()
147 		__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));  in dcache_wbinval_all()
148 		__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));  in dcache_wbinval_all()
149 		end -= line_size;  in dcache_wbinval_all()
150 		__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));  in dcache_wbinval_all()
151 		__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));  in dcache_wbinval_all()
152 		end -= line_size;  in dcache_wbinval_all()
153 		__asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));  in dcache_wbinval_all()
154 		__asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));  in dcache_wbinval_all()
156 	} while (end > 0);  in dcache_wbinval_all()
159 void flush_dcache_range(unsigned long start, unsigned long end)  in flush_dcache_range()  argument
165 	while (end > start) {  in flush_dcache_range()
174 void invalidate_dcache_range(unsigned long start, unsigned long end)  in invalidate_dcache_range()  argument
179 	while (end > start) {  in invalidate_dcache_range()
226 void flush_dcache_range(unsigned long start, unsigned long end)  in flush_dcache_range()  argument
230 void invalidate_dcache_range(unsigned long start, unsigned long end)  in invalidate_dcache_range()  argument