48 	u32 tmp;  in fsl_setup_serdes()  local
53 		tmp = in_be32(regs + FSL_SRDSCR0_OFFS);  in fsl_setup_serdes()
54 		tmp &= ~FSL_SRDSCR0_DPP_1V2;  in fsl_setup_serdes()
55 		out_be32(regs + FSL_SRDSCR0_OFFS, tmp);  in fsl_setup_serdes()
58 		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);  in fsl_setup_serdes()
59 		tmp &= ~FSL_SRDSCR2_VDD_1V2;  in fsl_setup_serdes()
60 		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);  in fsl_setup_serdes()
67 		tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);  in fsl_setup_serdes()
68 		tmp |= FSL_SRDSRSTCTL_SATA_RESET;  in fsl_setup_serdes()
69 		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);  in fsl_setup_serdes()
71 		tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;  in fsl_setup_serdes()
72 		out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);  in fsl_setup_serdes()
80 		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);  in fsl_setup_serdes()
81 		tmp &= ~FSL_SRDSCR1_PLLBW;  in fsl_setup_serdes()
82 		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);  in fsl_setup_serdes()
85 		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);  in fsl_setup_serdes()
86 		tmp &= ~FSL_SRDSCR2_SEIC_MASK;  in fsl_setup_serdes()
87 		tmp |= FSL_SRDSCR2_SEIC_SATA;  in fsl_setup_serdes()
88 		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);  in fsl_setup_serdes()
91 		tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |  in fsl_setup_serdes()
94 		out_be32(regs + FSL_SRDSCR3_OFFS, tmp);  in fsl_setup_serdes()
97 		tmp = rfcks | FSL_SRDSCR4_PROT_SATA;  in fsl_setup_serdes()
98 		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);  in fsl_setup_serdes()
103 		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);  in fsl_setup_serdes()
104 		tmp |= FSL_SRDSCR1_PLLBW;  in fsl_setup_serdes()
105 		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);  in fsl_setup_serdes()
108 		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);  in fsl_setup_serdes()
109 		tmp &= ~FSL_SRDSCR2_SEIC_MASK;  in fsl_setup_serdes()
110 		tmp |= FSL_SRDSCR2_SEIC_PEX;  in fsl_setup_serdes()
111 		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);  in fsl_setup_serdes()
114 		tmp = FSL_SRDSCR3_SDFM_SATA_PEX;  in fsl_setup_serdes()
115 		out_be32(regs + FSL_SRDSCR3_OFFS, tmp);  in fsl_setup_serdes()
118 		tmp = rfcks | FSL_SRDSCR4_PROT_PEX;  in fsl_setup_serdes()
120 			tmp |= FSL_SRDSCR4_PLANE_X2;  in fsl_setup_serdes()
121 		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);  in fsl_setup_serdes()
125 		tmp = in_be32(regs + FSL_SRDSCR1_OFFS);  in fsl_setup_serdes()
126 		tmp &= ~FSL_SRDSCR1_PLLBW;  in fsl_setup_serdes()
127 		out_be32(regs + FSL_SRDSCR1_OFFS, tmp);  in fsl_setup_serdes()
130 		tmp = in_be32(regs + FSL_SRDSCR2_OFFS);  in fsl_setup_serdes()
131 		tmp &= ~FSL_SRDSCR2_SEIC_MASK;  in fsl_setup_serdes()
132 		tmp |= FSL_SRDSCR2_SEIC_SGMII;  in fsl_setup_serdes()
133 		out_be32(regs + FSL_SRDSCR2_OFFS, tmp);  in fsl_setup_serdes()
139 		tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;  in fsl_setup_serdes()
140 		out_be32(regs + FSL_SRDSCR4_OFFS, tmp);  in fsl_setup_serdes()
147 	tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);  in fsl_setup_serdes()
148 	tmp |= FSL_SRDSRSTCTL_RST;  in fsl_setup_serdes()
149 	out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);  in fsl_setup_serdes()