43 	if (msr.lo & (1 << 0)) {  in enable_vmx()
55 	msr.lo = 0;  in enable_vmx()
76 		msr.lo |= (1 << 2);  in enable_vmx()
78 			msr.lo |= (1 << 1);  in enable_vmx()
172 	if (!(msr.lo & PLATFORM_INFO_SET_TDP))  in set_power_limits()
177 	power_unit = 2 << ((msr.lo & 0xf) - 1);  in set_power_limits()
181 	tdp = msr.lo & 0x7fff;  in set_power_limits()
182 	min_power = (msr.lo >> 16) & 0x7fff;  in set_power_limits()
200 	limit.lo = 0;  in set_power_limits()
201 	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;  in set_power_limits()
202 	limit.lo |= PKG_POWER_LIMIT_EN;  in set_power_limits()
203 	limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<  in set_power_limits()
218 		limit.lo = msr.lo & 0xff;  in set_power_limits()
229 	msr.lo |= (1 << 28);	/* C1 Auto Undemotion Enable */  in configure_c_states()
230 	msr.lo |= (1 << 27);	/* C3 Auto Undemotion Enable */  in configure_c_states()
231 	msr.lo |= (1 << 26);	/* C1 Auto Demotion Enable */  in configure_c_states()
232 	msr.lo |= (1 << 25);	/* C3 Auto Demotion Enable */  in configure_c_states()
233 	msr.lo &= ~(1 << 10);	/* Disable IO MWAIT redirection */  in configure_c_states()
234 	msr.lo |= 7;		/* No package C-state limit */  in configure_c_states()
238 	msr.lo &= ~0x7ffff;  in configure_c_states()
239 	msr.lo |= (PMB0_BASE + 4);	/* LVL_2 base address */  in configure_c_states()
240 	msr.lo |= (2 << 16);		/* CST Range: C7 is max C-state */  in configure_c_states()
244 	msr.lo &= ~(1 << 0);	/* Enable P-state HW_ALL coordination */  in configure_c_states()
248 	msr.lo |= (1 << 18);	/* Enable Energy Perf Bias MSR 0x1b0 */  in configure_c_states()
249 	msr.lo |= (1 << 1);	/* C1E Enable */  in configure_c_states()
250 	msr.lo |= (1 << 0);	/* Bi-directional PROCHOT# */  in configure_c_states()
255 	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;  in configure_c_states()
260 	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;  in configure_c_states()
265 	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;  in configure_c_states()
270 	msr.lo &= ~0x1fff;  in configure_c_states()
271 	msr.lo |= PP0_CURRENT_LIMIT;  in configure_c_states()
276 	msr.lo &= ~0x1fff;  in configure_c_states()
279 		msr.lo |= PP1_CURRENT_LIMIT_IVB;  in configure_c_states()
281 		msr.lo |= PP1_CURRENT_LIMIT_SNB;  in configure_c_states()
295 	if ((msr.lo & (1 << 30)) && tcc_offset) {  in configure_thermal_target()
297 		msr.lo &= ~(0xf << 24); /* Bits 27:24 */  in configure_thermal_target()
298 		msr.lo |= (tcc_offset & 0xf) << 24;  in configure_thermal_target()
310 	msr.lo |= (1 << 0);	  /* Fast String enable */  in configure_misc()
311 	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */  in configure_misc()
312 	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */  in configure_misc()
316 	msr.lo = 0;  in configure_misc()
321 	msr.lo = 1 << 4;  in configure_misc()
331 	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */  in enable_lapic_tpr()
344 		msr.lo |= 1;  in configure_dca_cap()
359 		perf_ctl.lo = (msr.lo & 0xff) << 8;  in set_max_ratio()
363 		perf_ctl.lo = msr.lo & 0xff00;  in set_max_ratio()
368 	      ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);  in set_max_ratio()
377 	msr.lo &= ~0xf;  in set_energy_perf_bias()
378 	msr.lo |= policy & 0xf;  in set_energy_perf_bias()
389 	msr.lo = 0;  in configure_mca()
442 	info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;  in model_206ax_get_info()