68 	u32 dtr0, dtr1, dtr2, dtr3, dtr4;  in prog_ddr_timing_control()  local
76 	dtr0 = msg_port_read(MEM_CTLR, DTR0);  in prog_ddr_timing_control()
98 	dtr0 &= ~DTR0_DFREQ_MASK;  in prog_ddr_timing_control()
99 	dtr0 |= mrc_params->ddr_speed;  in prog_ddr_timing_control()
100 	dtr0 &= ~DTR0_TCL_MASK;  in prog_ddr_timing_control()
102 	dtr0 |= ((tcl - 5) << 12);  in prog_ddr_timing_control()
103 	dtr0 &= ~DTR0_TRP_MASK;  in prog_ddr_timing_control()
104 	dtr0 |= ((trp - 5) << 4);	/* 5 bit DRAM Clock */  in prog_ddr_timing_control()
105 	dtr0 &= ~DTR0_TRCD_MASK;  in prog_ddr_timing_control()
106 	dtr0 |= ((trcd - 5) << 8);	/* 5 bit DRAM Clock */  in prog_ddr_timing_control()
166 	msg_port_write(MEM_CTLR, DTR0, dtr0);  in prog_ddr_timing_control()
1152 	u32 dtr0;  in perform_jedec_init()  local
1174 	dtr0 = msg_port_read(MEM_CTLR, DTR0);  in perform_jedec_init()
1292 	mrs0_cmd |= ((((dtr0 >> 12) & 7) + 1) << 10);  in perform_jedec_init()