Lines Matching refs:dtr1
68 u32 dtr0, dtr1, dtr2, dtr3, dtr4; in prog_ddr_timing_control() local
77 dtr1 = msg_port_read(MEM_CTLR, DTR1); in prog_ddr_timing_control()
108 dtr1 &= ~DTR1_TWCL_MASK; in prog_ddr_timing_control()
110 dtr1 |= (wl - 3); in prog_ddr_timing_control()
111 dtr1 &= ~DTR1_TWTP_MASK; in prog_ddr_timing_control()
112 dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */ in prog_ddr_timing_control()
113 dtr1 &= ~DTR1_TRTP_MASK; in prog_ddr_timing_control()
114 dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */ in prog_ddr_timing_control()
115 dtr1 &= ~DTR1_TRRD_MASK; in prog_ddr_timing_control()
116 dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ in prog_ddr_timing_control()
117 dtr1 &= ~DTR1_TCMD_MASK; in prog_ddr_timing_control()
118 dtr1 |= (1 << 4); in prog_ddr_timing_control()
119 dtr1 &= ~DTR1_TRAS_MASK; in prog_ddr_timing_control()
120 dtr1 |= ((tras - 14) << 20); /* 6 bit DRAM Clock */ in prog_ddr_timing_control()
121 dtr1 &= ~DTR1_TFAW_MASK; in prog_ddr_timing_control()
122 dtr1 |= ((((tfaw + 1) >> 1) - 5) << 16);/* 4 bit DRAM Clock */ in prog_ddr_timing_control()
124 dtr1 &= ~DTR1_TCCD_MASK; in prog_ddr_timing_control()
167 msg_port_write(MEM_CTLR, DTR1, dtr1); in prog_ddr_timing_control()
1423 u32 dtr1, dtr1_save; in rcvn_cal() local
1433 dtr1 = msg_port_read(MEM_CTLR, DTR1); in rcvn_cal()
1434 dtr1_save = dtr1; in rcvn_cal()
1435 dtr1 |= DTR1_TCCD_12CLK; in rcvn_cal()
1436 msg_port_write(MEM_CTLR, DTR1, dtr1); in rcvn_cal()