Lines Matching refs:DDR

23 DATA 0xFFD01400 0x43000618	# DDR Configuration register
26 # bit24: 1= enable exit self refresh mode on DDR access
31 DATA 0xFFD01404 0x35143000	# DDR Controller Control Low
42 DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
59 DATA 0xFFD01410 0x0000000C	#  DDR Address Control
74 DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000	#  DDR Operation
79 # bit3-0:   0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000632	#  DDR Mode
92 DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
93 # bit0:    0,  DDR DLL enabled
94 # bit1:    1,  DDR drive strenght reduced
95 # bit2:    1,  DDR ODT control lsd enabled
97 # bit6:    1,  DDR ODT control msb, enabled
101 # bit12:   0, DDR output buffer enabled
104 DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
109 # bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
131 DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
135 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
145 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
146 #bit0=1, enable DDR init upon this register write