Lines Matching refs:DDR

25 DATA 0xFFD01400 0x43000c30	# DDR Configuration register
28 # bit24: 1= enable exit self refresh mode on DDR access
33 DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
44 DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
55 DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
62 DATA 0xFFD01410 0x0000000d	#  DDR Address Control
77 DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
81 DATA 0xFFD01418 0x00000000	#  DDR Operation
82 # bit3-0:   0x0, DDR cmd
85 DATA 0xFFD0141C 0x00000C52	#  DDR Mode
95 DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
96 # bit0:    0,  DDR DLL enabled
97 # bit1:    0,  DDR drive strenght normal
98 # bit2:    0,  DDR ODT control lsd (disabled)
100 # bit6:    1,  DDR ODT control msb, (disabled)
104 # bit12:   0, DDR output buffer enabled
107 DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
112 # bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
136 DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
137 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
143 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
144 #bit0=1, enable DDR init upon this register write