Lines Matching refs:DDR

27 DATA 0xFFD01400 0x43000618	# DDR Configuration register
30 # bit24: 1= enable exit self refresh mode on DDR access
35 DATA 0xFFD01404 0x35143000	# DDR Controller Control Low
46 DATA 0xFFD01408 0x11012227	# DDR Timing (Low) (active cycles value +1)
56 DATA 0xFFD0140C 0x00000819	#  DDR Timing (High)
64 DATA 0xFFD01410 0x0000000d	#  DDR Address Control
79 DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
83 DATA 0xFFD01418 0x00000000	#  DDR Operation
84 # bit3-0:   0x0, DDR cmd
87 DATA 0xFFD0141C 0x00000632	#  DDR Mode
98 DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
99 # bit0:    0,  DDR DLL enabled
100 # bit1:    0,  DDR drive strenght normal
101 # bit2:    0,  DDR ODT control lsd (disabled)
103 # bit6:    1,  DDR ODT control msb, (disabled)
107 # bit12:   0, DDR output buffer enabled
110 DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
136 DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
137 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
144 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
145 #bit0=1, enable DDR init upon this register write