Lines Matching refs:ODT
114 # bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
116 # bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
136 # DDR2 ODT Read Timing (default values)
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
145 # DDR2 ODT Write Timing (default values)
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
177 # DDR ODT Control (Low)
186 # DDR ODT Control (High)
188 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
189 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
192 # CPU ODT Control
194 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
196 # bit9-8: 0, Internal ODT assertion is controlled by fiels
197 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
198 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
199 # bit14: 1, M_STARTBURST_IN ODT enabled
200 # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
201 # bit20-16: 0, Pad N channel driving strength for ODT
202 # bit25-21: 0, Pad P channel driving strength for ODT