Lines Matching refs:DDR

26 # DDR Configuration register
30 # bit24:    1, enable exit self refresh mode on DDR access
35 # DDR Controller Control Low
53 # DDR Timing (Low)
65 # DDR Timing (High)
73 # DDR Address Control
89 # DDR Open Pages Control
94 # DDR Operation
99 # DDR Mode
110 # DDR Extended Mode
123 # DDR Controller Control High
129 # bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
177 # DDR ODT Control (Low)
186 # DDR ODT Control (High)
200 # bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
205 # DDR Initialization Control
207 # bit0:     1, enable DDR init upon this register write