Lines Matching refs:DDR

26 DATA 0xffd01400 0x43000c30	# DDR Configuration register
29 # bit24: 1= enable exit self refresh mode on DDR access
34 DATA 0xffd01404 0x37543000	# DDR Controller Control Low
45 DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
56 DATA 0xffd0140c 0x00000a33	#  DDR Timing (High)
63 DATA 0xffd01410 0x000000cc	#  DDR Address Control
78 DATA 0xffd01414 0x00000000	#  DDR Open Pages Control
82 DATA 0xffd01418 0x00000000	#  DDR Operation
83 # bit3-0:   0x0, DDR cmd
86 DATA 0xffd0141c 0x00000c52	#  DDR Mode
96 DATA 0xffd01420 0x00000040	#  DDR Extended Mode
97 # bit0:    0,  DDR DLL enabled
98 # bit1:    0,  DDR drive strenght normal
99 # bit2:    0,  DDR ODT control lsd (disabled)
101 # bit6:    1,  DDR ODT control msb, (disabled)
105 # bit12:   0, DDR output buffer enabled
108 DATA 0xffd01424 0x0000f17f	#  DDR Controller Control High
113 # bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
137 DATA 0xffd01494 0x00030000	#  DDR ODT Control (Low)
143 DATA 0xffd01498 0x00000000	#  DDR ODT Control (High)
149 DATA 0xffd01480 0x00000001	# DDR Initialization Control
150 #bit0=1, enable DDR init upon this register write