Lines Matching refs:MUX_VAL
16 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
17 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
18 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
19 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
20 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
21 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
22 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
23 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
24 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
25 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
26 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
27 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
28 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
29 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
30 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
31 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
32 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
33 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
34 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
35 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
36 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
37 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
38 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
39 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
40 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
41 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
42 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
43 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
44 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
45 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
46 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
47 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
48 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
49 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
50 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
51 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
52 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
53 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
54 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); in set_muxconf_regs()
57 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
58 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
59 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
60 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
61 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
62 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
63 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
64 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
65 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
66 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
67 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); in set_muxconf_regs()
68 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); in set_muxconf_regs()
69 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); in set_muxconf_regs()
70 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); in set_muxconf_regs()
71 MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); in set_muxconf_regs()
72 MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); in set_muxconf_regs()
73 MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); in set_muxconf_regs()
74 MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); in set_muxconf_regs()
75 MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); in set_muxconf_regs()
76 MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); in set_muxconf_regs()
77 MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); in set_muxconf_regs()
78 MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); in set_muxconf_regs()
79 MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); in set_muxconf_regs()
80 MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); in set_muxconf_regs()
81 MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); in set_muxconf_regs()
82 MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); in set_muxconf_regs()
83 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
86 MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); in set_muxconf_regs()
88 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ in set_muxconf_regs()
90 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ in set_muxconf_regs()
93 MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ in set_muxconf_regs()
94 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
95 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
96 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
97 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
99 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ in set_muxconf_regs()
100 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
101 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); in set_muxconf_regs()
103 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ in set_muxconf_regs()
106 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
107 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
109 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ in set_muxconf_regs()
111 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ in set_muxconf_regs()
114 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ in set_muxconf_regs()
116 MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ in set_muxconf_regs()
118 MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ in set_muxconf_regs()
120 MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/ in set_muxconf_regs()
123 MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)); in set_muxconf_regs()
124 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)); in set_muxconf_regs()
125 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)); in set_muxconf_regs()
126 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)); in set_muxconf_regs()
127 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)); in set_muxconf_regs()
128 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)); in set_muxconf_regs()
131 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
132 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
133 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
134 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
135 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
136 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
137 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
138 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
139 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
140 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
141 MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
142 MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
143 MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
144 MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
145 MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
146 MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
147 MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
148 MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
149 MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
150 MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
151 MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
152 MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
153 MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
154 MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
155 MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
156 MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
157 MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
158 MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); in set_muxconf_regs()
161 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); in set_muxconf_regs()
162 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); in set_muxconf_regs()
163 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); in set_muxconf_regs()
164 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); in set_muxconf_regs()
167 MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/ in set_muxconf_regs()
169 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ in set_muxconf_regs()
172 MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0)); in set_muxconf_regs()
173 MUX_VAL(CP(RMII_MDIO_CLK), (M0)); in set_muxconf_regs()
174 MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
175 MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
176 MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
177 MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0)); in set_muxconf_regs()
178 MUX_VAL(CP(RMII_TXD0), (IDIS | M0)); in set_muxconf_regs()
179 MUX_VAL(CP(RMII_TXD1), (IDIS | M0)); in set_muxconf_regs()
180 MUX_VAL(CP(RMII_TXEN), (IDIS | M0)); in set_muxconf_regs()
181 MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0)); in set_muxconf_regs()
184 MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/ in set_muxconf_regs()
187 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ in set_muxconf_regs()
188 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ in set_muxconf_regs()
189 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ in set_muxconf_regs()
190 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ in set_muxconf_regs()
192 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ in set_muxconf_regs()
195 MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/ in set_muxconf_regs()
197 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/ in set_muxconf_regs()
200 MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)); in set_muxconf_regs()
202 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ in set_muxconf_regs()
203 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ in set_muxconf_regs()
204 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ in set_muxconf_regs()
205 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ in set_muxconf_regs()
206 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ in set_muxconf_regs()
207 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ in set_muxconf_regs()
208 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ in set_muxconf_regs()
209 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ in set_muxconf_regs()
210 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ in set_muxconf_regs()
211 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ in set_muxconf_regs()
212 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ in set_muxconf_regs()
213 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ in set_muxconf_regs()
215 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ in set_muxconf_regs()
216 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ in set_muxconf_regs()
217 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ in set_muxconf_regs()
218 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ in set_muxconf_regs()
219 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ in set_muxconf_regs()
220 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ in set_muxconf_regs()
221 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ in set_muxconf_regs()
222 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ in set_muxconf_regs()
223 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ in set_muxconf_regs()
224 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ in set_muxconf_regs()
225 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ in set_muxconf_regs()
226 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ in set_muxconf_regs()
229 MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/ in set_muxconf_regs()
230 MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/ in set_muxconf_regs()
231 MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/ in set_muxconf_regs()
232 MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/ in set_muxconf_regs()
233 MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/ in set_muxconf_regs()
234 MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/ in set_muxconf_regs()