Lines Matching refs:DDR

26 DATA 0xFFD01400 0x43000c30	# DDR Configuration register
29 # bit24:    1, enable exit self refresh mode on DDR access
34 DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
51 DATA 0xFFD01408 0x22125451	# DDR Timing (Low)
62 DATA 0xFFD0140C 0x00000833	#  DDR Timing (High)
69 DATA 0xFFD01410 0x0000000c	#  DDR Address Control
84 DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
88 DATA 0xFFD01418 0x00000000	#  DDR Operation
92 DATA 0xFFD0141C 0x00000C52	#  DDR Mode
102 DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
114 DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
119 # bit8:     1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
160 DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
168 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
180 # bit15:    1, DDR IO ODT Unit: Drive ODT calibration values
185 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
186 # bit0:     1, enable DDR init upon this register write