Lines Matching refs:t0
27 li t0, MEM_STCFG2
29 sw t1, 0(t0)
31 li t0, MEM_STTIME2
33 sw t1, 0(t0)
35 li t0, MEM_STADDR2
37 sw t1, 0(t0)
39 li t0, MEM_STCFG1
41 sw t1, 0(t0)
43 li t0, MEM_STTIME1
45 sw t1, 0(t0)
47 li t0, MEM_STADDR1
49 sw t1, 0(t0)
52 li t0, DB1XX0_BCSR_ADDR
53 lw t1,8(t0)
60 li t0, AU1500_SYS_ADDR
62 sw t1, sys_endian(t0)
117 lui t0, 0xffc0
119 and t1, ra, t0
127 li t0, (16*1024)
130 addu t3, t0, t2
146 and t0, ra, t1
147 addi t0, 5*4 /* 5 insns beyond cachehere */
148 jr t0
157 li t0, 0 # index value
176 mtc0 t0, CP0_INDEX
183 addiu t0, t0, 1
184 bne t0, t2, tlbloop
191 li t0, SYS_CPUPLL
193 sw t1, 0(t0)
204 li t0, SYS_AUXPLL
206 sw t1, 0(t0) /* aux pll */
228 li t0, MEM_STTIME0
230 sw t1, 0(t0)
233 li t0, MEM_STCFG0
235 sw t1, 0(t0)
237 li t0, MEM_STADDR0
239 sw t1, 0(t0)
241 li t0, MEM_STTIME0
243 sw t1, 0(t0)
246 li t0, MEM_STCFG0
248 sw t1, 0(t0)
250 li t0, MEM_STADDR0
252 sw t1, 0(t0)
256 li t0, MEM_STCFG1
258 sw t1, 0(t0)
260 li t0, MEM_STTIME1
262 sw t1, 0(t0)
264 li t0, MEM_STADDR1
266 sw t1, 0(t0)
270 li t0, MEM_STCFG2
272 sw t1, 0(t0)
274 li t0, MEM_STTIME2
276 sw t1, 0(t0)
278 li t0, MEM_STADDR2
280 sw t1, 0(t0)
282 li t0, MEM_STCFG2
284 sw t1, 0(t0)
286 li t0, MEM_STTIME2
288 sw t1, 0(t0)
290 li t0, MEM_STADDR2
292 sw t1, 0(t0)
296 li t0, MEM_STCFG3
298 sw t1, 0(t0)
300 li t0, MEM_STTIME3
302 sw t1, 0(t0)
304 li t0, MEM_STADDR3
306 sw t1, 0(t0)
311 li t0, IC0_CFG0CLR
313 sw t1, 0(t0)
315 li t0, IC0_CFG0CLR
316 sw t1, 0(t0)
318 li t0, IC0_CFG1CLR
319 sw t1, 0(t0)
321 li t0, IC0_CFG2CLR
322 sw t1, 0(t0)
324 li t0, IC0_SRCSET
325 sw t1, 0(t0)
327 li t0, IC0_ASSIGNSET
328 sw t1, 0(t0)
330 li t0, IC0_WAKECLR
331 sw t1, 0(t0)
333 li t0, IC0_RISINGCLR
334 sw t1, 0(t0)
336 li t0, IC0_FALLINGCLR
337 sw t1, 0(t0)
339 li t0, IC0_TESTBIT
341 sw t1, 0(t0)
344 li t0, IC1_CFG0CLR
346 sw t1, 0(t0)
348 li t0, IC1_CFG0CLR
349 sw t1, 0(t0)
351 li t0, IC1_CFG1CLR
352 sw t1, 0(t0)
354 li t0, IC1_CFG2CLR
355 sw t1, 0(t0)
357 li t0, IC1_SRCSET
358 sw t1, 0(t0)
360 li t0, IC1_ASSIGNSET
361 sw t1, 0(t0)
363 li t0, IC1_WAKECLR
364 sw t1, 0(t0)
366 li t0, IC1_RISINGCLR
367 sw t1, 0(t0)
369 li t0, IC1_FALLINGCLR
370 sw t1, 0(t0)
372 li t0, IC1_TESTBIT
374 sw t1, 0(t0)
377 li t0, SYS_FREQCTRL0
379 sw t1, 0(t0)
381 li t0, SYS_FREQCTRL1
383 sw t1, 0(t0)
385 li t0, SYS_CLKSRC
387 sw t1, 0(t0)
389 li t0, SYS_PININPUTEN
391 sw t1, 0(t0)
394 li t0, 0xB1100100
396 sw t1, 0(t0)
398 li t0, 0xB1400100
400 sw t1, 0(t0)
403 li t0, SYS_WAKEMSK
405 sw t1, 0(t0)
407 li t0, SYS_WAKESRC
409 sw t1, 0(t0)
419 li t0, MEM_SDMODE0
421 sw t1, 0(t0)
423 li t0, MEM_SDMODE1
425 sw t1, 0(t0)
427 li t0, MEM_SDMODE2
429 sw t1, 0(t0)
431 li t0, MEM_SDADDR0
433 sw t1, 0(t0)
435 li t0, MEM_SDADDR1
437 sw t1, 0(t0)
439 li t0, MEM_SDADDR2
441 sw t1, 0(t0)
445 li t0, MEM_SDCONFIGA
447 sw t1, 0(t0)
450 li t0, MEM_SDCONFIGB
452 sw t1, 0(t0)
455 li t0, MEM_SDPRECMD /* Precharge all */
457 sw t1, 0(t0)
460 li t0, MEM_SDWRMD0
462 sw t1, 0(t0)
465 li t0, MEM_SDWRMD1
467 sw t1, 0(t0)
470 li t0, MEM_SDWRMD2
472 sw t1, 0(t0)
475 li t0, MEM_SDWRMD0
477 sw t1, 0(t0)
480 li t0, MEM_SDWRMD1
482 sw t1, 0(t0)
485 li t0, MEM_SDWRMD2
487 sw t1, 0(t0)
490 li t0, MEM_SDPRECMD /* Precharge all */
491 sw zero, 0(t0)
495 li t0, MEM_SDAUTOREF
496 sw zero, 0(t0)
499 li t0, MEM_SDAUTOREF
500 sw zero, 0(t0)
504 li t0, MEM_SDCONFIGA
506 sw t1, 0(t0)
511 li t0, MEM_SDMODE0
513 sw t1, 0(t0)
515 li t0, MEM_SDMODE1
517 sw t1, 0(t0)
519 li t0, MEM_SDMODE2
521 sw t1, 0(t0)
523 li t0, MEM_SDADDR0
525 sw t1, 0(t0)
528 li t0, MEM_SDADDR1
530 sw t1, 0(t0)
532 li t0, MEM_SDADDR2
534 sw t1, 0(t0)
538 li t0, MEM_SDREFCFG
540 sw t1, 0(t0)
543 li t0, MEM_SDPRECMD
544 sw zero, 0(t0)
547 li t0, MEM_SDAUTOREF
548 sw zero, 0(t0)
550 sw zero, 0(t0)
553 li t0, MEM_SDREFCFG
555 sw t1, 0(t0)
558 li t0, MEM_SDWRMD0
560 sw t1, 0(t0)
563 li t0, MEM_SDWRMD1
565 sw t1, 0(t0)
575 li t0, SYS_PINFUNC
577 sw t1, 0(t0)
579 li t0, SYS_TRIOUTCLR
581 sw t1, 0(t0)
583 li t0, SYS_OUTPUTCLR
585 sw t1, 0(t0)