Lines Matching refs:vid
284 u8 vid; in set_voltage_to_IR() local
291 vid = DIV_ROUND_UP(vdd - 265, 5); in set_voltage_to_IR()
293 vid = DIV_ROUND_UP(vdd - 245, 5); in set_voltage_to_IR()
297 1, (void *)&vid, sizeof(vid)); in set_voltage_to_IR()
374 u8 vid, buf; in adjust_vdd() local
376 u8 vid; in adjust_vdd() local
455 u8 vid; in adjust_vdd() member
495 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
497 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
498 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
501 vdd_target = vdd[vid]; in adjust_vdd()
593 u8 vid, buf; in adjust_vdd() local
627 u8 vid; in adjust_vdd() member
685 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
687 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
688 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
692 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & in adjust_vdd()
694 if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { in adjust_vdd()
695 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & in adjust_vdd()
699 vdd_target = vdd[vid]; in adjust_vdd()