52 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);  in ddrmc_init()
54 	out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);  in ddrmc_init()
55 	out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);  in ddrmc_init()
57 	out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);  in ddrmc_init()
58 	out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);  in ddrmc_init()
59 	out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);  in ddrmc_init()
60 	out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);  in ddrmc_init()
61 	out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);  in ddrmc_init()
62 	out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);  in ddrmc_init()
64 	out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);  in ddrmc_init()
65 	out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);  in ddrmc_init()
67 	out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);  in ddrmc_init()
68 	out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);  in ddrmc_init()
70 	out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);  in ddrmc_init()
72 	out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);  in ddrmc_init()
74 	out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);  in ddrmc_init()
75 	out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);  in ddrmc_init()
77 	out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);  in ddrmc_init()
79 	out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);  in ddrmc_init()
80 	out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);  in ddrmc_init()
82 	out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);  in ddrmc_init()
86 	out_be32(&ddr->debug[28], tmp | 0x0070006f);  in ddrmc_init()
92 	out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);  in ddrmc_init()
164 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);  in board_early_init_f()