17 void fsl_ddr_board_options(memctl_options_t *popts,  in fsl_ddr_board_options()  argument
40 				popts->clk_adjust = pbsp->clk_adjust;  in fsl_ddr_board_options()
41 				popts->wrlvl_start = pbsp->wrlvl_start;  in fsl_ddr_board_options()
42 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
43 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
44 				popts->cpo_override = pbsp->cpo_override;  in fsl_ddr_board_options()
45 				popts->write_data_delay =  in fsl_ddr_board_options()
59 		popts->clk_adjust = pbsp_highest->clk_adjust;  in fsl_ddr_board_options()
60 		popts->wrlvl_start = pbsp_highest->wrlvl_start;  in fsl_ddr_board_options()
61 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
62 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
71 	popts->data_bus_width = 1;  in fsl_ddr_board_options()
72 	popts->otf_burst_chop_en = 0;  in fsl_ddr_board_options()
73 	popts->burst_length = DDR_BL8;  in fsl_ddr_board_options()
74 	popts->bstopre = 0;		/* enable auto precharge */  in fsl_ddr_board_options()
80 	popts->half_strength_driver_enable = 1;  in fsl_ddr_board_options()
84 	popts->wrlvl_override = 1;  in fsl_ddr_board_options()
85 	popts->wrlvl_sample = 0xf;  in fsl_ddr_board_options()
90 	popts->rtt_override = 0;  in fsl_ddr_board_options()
93 	popts->zq_en = 1;  in fsl_ddr_board_options()
96 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);  in fsl_ddr_board_options()
97 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |  in fsl_ddr_board_options()
101 	popts->cpo_sample = 0x59;  in fsl_ddr_board_options()
103 	popts->cswl_override = DDR_CSWL_CS0;  in fsl_ddr_board_options()
106 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);  in fsl_ddr_board_options()
107 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);  in fsl_ddr_board_options()