Lines Matching +full:cycle +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0
17 * - number of chips on bus in fsl_ddr_board_options()
18 * - position of slot in fsl_ddr_board_options()
19 * - DDR1 vs. DDR2? in fsl_ddr_board_options()
20 * - ??? in fsl_ddr_board_options()
22 * This needs to be determined on a board-by-board basis. in fsl_ddr_board_options()
23 * 0110 3/4 cycle late in fsl_ddr_board_options()
24 * 0111 7/8 cycle late in fsl_ddr_board_options()
26 popts->clk_adjust = 4; in fsl_ddr_board_options()
30 * - frequency in fsl_ddr_board_options()
31 * - ddr1 vs. ddr2 in fsl_ddr_board_options()
33 popts->cpo_override = 0xff; in fsl_ddr_board_options()
37 * - number of DIMMs in fsl_ddr_board_options()
46 popts->write_data_delay = 2; in fsl_ddr_board_options()
51 popts->half_strength_driver_enable = 1; in fsl_ddr_board_options()
54 popts->wrlvl_en = 1; in fsl_ddr_board_options()
55 popts->wrlvl_override = 1; in fsl_ddr_board_options()
56 popts->wrlvl_sample = 0xa; in fsl_ddr_board_options()
57 popts->wrlvl_start = 0x4; in fsl_ddr_board_options()
60 popts->rtt_override = 1; in fsl_ddr_board_options()
61 popts->rtt_override_value = DDR3_RTT_60_OHM; in fsl_ddr_board_options()
62 popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ in fsl_ddr_board_options()