24 static void dp501_setbits(u8 addr, u8 reg, u8 mask)  in dp501_setbits()  argument
28 	val = i2c_reg_read(addr, reg);  in dp501_setbits()
30 	i2c_reg_write(addr, reg, val);  in dp501_setbits()
33 static void dp501_clrbits(u8 addr, u8 reg, u8 mask)  in dp501_clrbits()  argument
37 	val = i2c_reg_read(addr, reg);  in dp501_clrbits()
39 	i2c_reg_write(addr, reg, val);  in dp501_clrbits()
42 static int dp501_detect_cable_adapter(u8 addr)  in dp501_detect_cable_adapter()  argument
44 	u8 val = i2c_reg_read(addr, 0x00);  in dp501_detect_cable_adapter()
49 static void dp501_link_training(u8 addr)  in dp501_link_training()  argument
56 	val = i2c_reg_read(addr, 0x51);  in dp501_link_training()
64 	i2c_reg_write(addr, 0x5d, link_bw); /* set link_bw */  in dp501_link_training()
65 	val = i2c_reg_read(addr, 0x52);  in dp501_link_training()
74 	i2c_reg_write(addr, 0x5e, lane_cnt | (val & 0x80)); /* set lane_cnt */  in dp501_link_training()
75 	val = i2c_reg_read(addr, 0x53);  in dp501_link_training()
76 	i2c_reg_write(addr, 0x5c, val); /* set downspread_ctl */  in dp501_link_training()
78 	i2c_reg_write(addr, 0x5f, 0x0d); /* start training */  in dp501_link_training()
81 void dp501_powerup(u8 addr)  in dp501_powerup()  argument
83 	dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */  in dp501_powerup()
84 	dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/  in dp501_powerup()
85 	i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */  in dp501_powerup()
86 	dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */  in dp501_powerup()
87 	dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */  in dp501_powerup()
88 	i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */  in dp501_powerup()
89 	dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */  in dp501_powerup()
90 	dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */  in dp501_powerup()
91 	dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */  in dp501_powerup()
94 	i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);  in dp501_powerup()
96 	i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */  in dp501_powerup()
100 	i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */  in dp501_powerup()
101 	i2c_reg_write(addr + 2, 0x25, 0x04);  in dp501_powerup()
102 	i2c_reg_write(addr + 2, 0x26, 0x10);  in dp501_powerup()
104 	i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */  in dp501_powerup()
107 	i2c_reg_write(addr + 2, 0x1a, 0x04); /* SPDIF input method TTL */  in dp501_powerup()
109 	i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */  in dp501_powerup()
110 	i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */  in dp501_powerup()
111 	i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */  in dp501_powerup()
112 	i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */  in dp501_powerup()
113 	i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */  in dp501_powerup()
114 	i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */  in dp501_powerup()
115 	dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */  in dp501_powerup()
116 	i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */  in dp501_powerup()
117 	i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */  in dp501_powerup()
118 	i2c_reg_write(addr, 0x87, 0x7f); /* set retry counter as 7  in dp501_powerup()
121 	if (dp501_detect_cable_adapter(addr)) {  in dp501_powerup()
123 		i2c_reg_write(addr, 0x5e, 0x04); /* enable 4 channel */  in dp501_powerup()
124 		dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */  in dp501_powerup()
127 		dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */  in dp501_powerup()
129 		dp501_link_training(addr);  in dp501_powerup()
133 void dp501_powerdown(u8 addr)  in dp501_powerdown()  argument
135 	dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */  in dp501_powerdown()