Lines Matching refs:DDR

48 # bit24: 1= enable exit self refresh mode on DDR access
53 DATA 0xFFD01404 0x38543000	# DDR Controller Control Low
65 DATA 0xFFD01408 0x2302433E	# DDR Timing (Low) (active cycles value +1)
76 DATA 0xFFD0140C 0x00000A3E	#  DDR Timing (High)
83 DATA 0xFFD01410 0x00000001	#  DDR Address Control
98 DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
102 DATA 0xFFD01418 0x00000000	#  DDR Operation
103 # bit3-0:   0x0, DDR cmd
106 DATA 0xFFD0141C 0x00000652	#  DDR Mode
107 DATA 0xFFD01420 0x00000006	#  DDR Extended Mode
108 # bit0:    0,  DDR DLL enabled
109 # bit1:    1,  DDR drive strenght reduced
110 # bit2:    1,  DDR ODT control lsd disabled
112 # bit6:    0,  DDR ODT control msb disabled
116 # bit12:   0, DDR output buffer enabled
119 DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
157 DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
161 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
175 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
176 # bit0=1, enable DDR init upon this register write