Lines Matching refs:DDR

45 # bit24: 1= enable exit self refresh mode on DDR access
50 DATA 0xFFD01404 0x39543000	# DDR Controller Control Low
62 DATA 0xFFD01408 0x34136552	# DDR Timing (Low) (active cycles value +1)
73 DATA 0xFFD0140C 0x00000033	#  DDR Timing (High)
80 DATA 0xFFD01410 0x0000000D	#  DDR Address Control
95 DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
99 DATA 0xFFD01418 0x00000000	#  DDR Operation
100 # bit3-0:   0x0, DDR cmd
103 DATA 0xFFD0141C 0x00000652	#  DDR Mode
104 DATA 0xFFD01420 0x00000044	#  DDR Extended Mode
105 # bit0:    0,  DDR DLL enabled
106 # bit1:    0,  DDR drive strenght normal
107 # bit2:    1,  DDR ODT control lsd disabled
109 # bit6:    1,  DDR ODT control msb, enabled
113 # bit12:   0, DDR output buffer enabled
116 DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
142 DATA 0xFFD01494 0x00010001	#  DDR ODT Control (Low)
146 DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
157 DATA 0xFFD01480 0x00000001	# DDR Initialization Control
158 # bit0=1, enable DDR init upon this register write