Lines Matching refs:en1
17 union dcgu_clk_en1 en1; in dcgu_set_clk_switch() local
36 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); in dcgu_set_clk_switch()
40 en1.bits.en_clkmsmc = enable; in dcgu_set_clk_switch()
43 en1.bits.en_clkssi_s = enable; in dcgu_set_clk_switch()
46 en1.bits.en_clkssi_m = enable; in dcgu_set_clk_switch()
49 en1.bits.en_clksmc = enable; in dcgu_set_clk_switch()
52 en1.bits.en_clkebi = enable; in dcgu_set_clk_switch()
55 en1.bits.en_usbpll = enable; in dcgu_set_clk_switch()
58 en1.bits.en_clkusb60 = enable; in dcgu_set_clk_switch()
61 en1.bits.en_clkusb24 = enable; in dcgu_set_clk_switch()
64 en1.bits.en_clkuart2 = enable; in dcgu_set_clk_switch()
67 en1.bits.en_clkuart1 = enable; in dcgu_set_clk_switch()
70 en1.bits.en_clkperi20 = enable; in dcgu_set_clk_switch()
76 en1.bits.en_clk_i2s_dly = enable; in dcgu_set_clk_switch()
79 en1.bits.en_clk_scc_abp = enable; in dcgu_set_clk_switch()
82 en1.bits.en_clk_dtv_spdo = enable; in dcgu_set_clk_switch()
85 en1.bits.en_clkad = enable; in dcgu_set_clk_switch()
88 en1.bits.en_clkmvd = enable; in dcgu_set_clk_switch()
91 en1.bits.en_clktsd = enable; in dcgu_set_clk_switch()
94 en1.bits.en_clkga = enable; in dcgu_set_clk_switch()
97 en1.bits.en_clkdvp = enable; in dcgu_set_clk_switch()
100 en1.bits.en_clkmr2 = enable; in dcgu_set_clk_switch()
103 en1.bits.en_clkmr1 = enable; in dcgu_set_clk_switch()
122 reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg); in dcgu_set_clk_switch()
123 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); in dcgu_set_clk_switch()