Lines Matching refs:t0
27 li t0, MEM_STCFG1
29 sw t1, 0(t0)
31 li t0, MEM_STTIME1
33 sw t1, 0(t0)
35 li t0, MEM_STADDR1
37 sw t1, 0(t0)
55 li t0, AU1500_SYS_ADDR
57 sw t1, sys_endian(t0)
112 li t0, SYS_CPUPLL
114 sw t1, 0(t0)
125 li t0, SYS_AUXPLL
127 sw t1, 0(t0) /* aux pll */
133 li t0, MEM_STCFG0
135 sw t1, 0(t0)
137 li t0, MEM_STTIME0
139 sw t1, 0(t0)
141 li t0, MEM_STADDR0
143 sw t1, 0(t0)
146 li t0, MEM_STCFG1
148 sw t1, 0(t0)
150 li t0, MEM_STTIME1
152 sw t1, 0(t0)
154 li t0, MEM_STADDR1
156 sw t1, 0(t0)
159 li t0, MEM_STCFG2
161 sw t1, 0(t0)
163 li t0, MEM_STTIME2
165 sw t1, 0(t0)
167 li t0, MEM_STADDR2
169 sw t1, 0(t0)
172 li t0, MEM_STCFG3
174 sw t1, 0(t0)
176 li t0, MEM_STTIME3
178 sw t1, 0(t0)
180 li t0, MEM_STADDR3
182 sw t1, 0(t0)
187 li t0, IC0_CFG0CLR
189 sw t1, 0(t0)
191 li t0, IC0_CFG0CLR
192 sw t1, 0(t0)
194 li t0, IC0_CFG1CLR
195 sw t1, 0(t0)
197 li t0, IC0_CFG2CLR
198 sw t1, 0(t0)
200 li t0, IC0_SRCSET
201 sw t1, 0(t0)
203 li t0, IC0_ASSIGNSET
204 sw t1, 0(t0)
206 li t0, IC0_WAKECLR
207 sw t1, 0(t0)
209 li t0, IC0_RISINGCLR
210 sw t1, 0(t0)
212 li t0, IC0_FALLINGCLR
213 sw t1, 0(t0)
215 li t0, IC0_TESTBIT
217 sw t1, 0(t0)
220 li t0, IC1_CFG0CLR
222 sw t1, 0(t0)
224 li t0, IC1_CFG0CLR
225 sw t1, 0(t0)
227 li t0, IC1_CFG1CLR
228 sw t1, 0(t0)
230 li t0, IC1_CFG2CLR
231 sw t1, 0(t0)
233 li t0, IC1_SRCSET
234 sw t1, 0(t0)
236 li t0, IC1_ASSIGNSET
237 sw t1, 0(t0)
239 li t0, IC1_WAKECLR
240 sw t1, 0(t0)
242 li t0, IC1_RISINGCLR
243 sw t1, 0(t0)
245 li t0, IC1_FALLINGCLR
246 sw t1, 0(t0)
248 li t0, IC1_TESTBIT
250 sw t1, 0(t0)
253 li t0, SYS_FREQCTRL0
255 sw t1, 0(t0)
257 li t0, SYS_FREQCTRL1
259 sw t1, 0(t0)
261 li t0, SYS_CLKSRC
263 sw t1, 0(t0)
265 li t0, SYS_PININPUTEN
267 sw t1, 0(t0)
270 li t0, 0xB1100100
272 sw t1, 0(t0)
274 li t0, 0xB1400100
276 sw t1, 0(t0)
279 li t0, SYS_WAKEMSK
281 sw t1, 0(t0)
283 li t0, SYS_WAKESRC
285 sw t1, 0(t0)
296 li t0, 0x90000000
297 sub t0, ra, t0
298 bltz t0, skip_memsetup
306 li t0, MEM_SDMODE0
308 sw t1, 0(t0)
310 li t0, MEM_SDMODE1
312 sw t1, 0(t0)
314 li t0, MEM_SDMODE2
316 sw t1, 0(t0)
318 li t0, MEM_SDADDR0
320 sw t1, 0(t0)
322 li t0, MEM_SDADDR1
324 sw t1, 0(t0)
326 li t0, MEM_SDADDR2
328 sw t1, 0(t0)
332 li t0, MEM_SDREFCFG
334 sw t1, 0(t0)
337 li t0, MEM_SDPRECMD
338 sw zero, 0(t0)
341 li t0, MEM_SDAUTOREF
342 sw zero, 0(t0)
344 sw zero, 0(t0)
347 li t0, MEM_SDREFCFG
349 sw t1, 0(t0)
352 li t0, MEM_SDWRMD0
354 sw t1, 0(t0)
357 li t0, MEM_SDWRMD1
359 sw t1, 0(t0)
362 li t0, MEM_SDWRMD2
364 sw t1, 0(t0)
375 li t0, SYS_PINFUNC
377 sw t1, 0(t0)