Lines Matching refs:DDR

23 DATA 0xffd01400 0x43000c30	# DDR Configuration register
26 # bit24:    0x1,   enable exit self refresh mode on DDR access
31 DATA 0xffd01404 0x37543000	# DDR Controller Control Low
42 DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
53 DATA 0xffd0140c 0x00000a33	# DDR Timing (High)
60 DATA 0xffd01410 0x0000000c	# DDR Address Control
75 DATA 0xffd01414 0x00000000	# DDR Open Pages Control
79 DATA 0xffd01418 0x00000000	# DDR Operation
80 # bit3-0:   0x0, DDR cmd
83 DATA 0xffd0141c 0x00000c52	# DDR Mode
93 DATA 0xffd01420 0x00000040	# DDR Extended Mode
94 # bit0:     0,   DDR DLL enabled
95 # bit1:     0,   DDR drive strenght normal
96 # bit2:     1,   DDR ODT control lsd (disabled)
98 # bit6:     0,   DDR ODT control msb, (disabled)
102 # bit12:    0,   DDR output buffer enabled
105 DATA 0xffd01424 0x0000f17f	# DDR Controller Control High
110 # bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
134 DATA 0xffd01494 0x00030000	# DDR ODT Control (Low)
140 DATA 0xffd01498 0x00000000	# DDR ODT Control (High)
146 DATA 0xffd01480 0x00000001	# DDR Initialization Control
147 # bit0: 0x1, enable DDR init upon this register write