Lines Matching refs:spi_write
59 #define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val macro
74 spi_write(0x00, CR3); in spi_reset()
75 spi_write(0x02, CR1); in spi_reset()
80 spi_write(0x00, CR1); in spi_reset()
82 spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ in spi_reset()
83 spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); in spi_reset()
85 spi_write(0, SPIDMCOR); in spi_reset()
91 spi_write(CR7_IDX_OR12, CR7); in spi_read_flash()
94 spi_write(M25_READ_4BYTE, TBR); in spi_read_flash()
95 spi_write((addr >> 24) & 0xFF, TBR); /* ADDR31-24 */ in spi_read_flash()
98 spi_write(M25_READ, TBR); in spi_read_flash()
100 spi_write((addr >> 16) & 0xFF, TBR); /* ADDR23-16 */ in spi_read_flash()
101 spi_write((addr >> 8) & 0xFF, TBR); /* ADDR15-8 */ in spi_read_flash()
102 spi_write(addr & 0xFF, TBR); /* ADDR7-0 */ in spi_read_flash()
104 spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); in spi_read_flash()
105 spi_write((unsigned long)buf, SPIWDMADR); in spi_read_flash()
106 spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); in spi_read_flash()
107 spi_write(1, SPIDMCOR); in spi_read_flash()
109 spi_write(0xff, CR3); in spi_read_flash()
110 spi_write(spi_read(CR1) | SPI_SSDB, CR1); in spi_read_flash()
111 spi_write(spi_read(CR1) | SPI_SSA, CR1); in spi_read_flash()
117 spi_write(0, CR1); in spi_read_flash()