Lines Matching refs:clr
95 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; in board_clock_init() local
151 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | in board_clock_init()
155 clrsetbits_le32(&clk->div_cpu0, clr, set); in board_clock_init()
167 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); in board_clock_init()
170 clrsetbits_le32(&clk->div_cpu1, clr, set); in board_clock_init()
223 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | in board_clock_init()
240 clrsetbits_le32(&clk->div_dmc0, clr, set); in board_clock_init()
247 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | in board_clock_init()
263 clrsetbits_le32(&clk->div_dmc1, clr, set); in board_clock_init()
270 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | in board_clock_init()
283 clrsetbits_le32(&clk->src_peril0, clr, set); in board_clock_init()
286 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | in board_clock_init()
296 clrsetbits_le32(&clk->div_peril0, clr, set); in board_clock_init()
302 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | in board_clock_init()
315 clrsetbits_le32(&clk->div_fsys1, clr, set); in board_clock_init()
322 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | in board_clock_init()
335 clrsetbits_le32(&clk->div_fsys2, clr, set); in board_clock_init()
342 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); in board_clock_init()
351 clrsetbits_le32(&clk->div_fsys3, clr, set); in board_clock_init()