Lines Matching full:offset
26 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
27 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
32 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
33 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
38 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
39 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
44 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
45 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
50 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
51 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
56 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
57 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
62 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
63 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
64 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
65 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
66 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
67 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
68 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
69 {OFFSET(spi0_cs1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* GPIO0_6 */
74 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
75 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
76 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
77 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
78 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
79 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
80 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
85 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
86 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
87 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
88 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
89 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
90 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
91 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
96 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
97 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
98 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
99 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
100 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
101 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
102 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
103 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
108 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
110 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
116 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
118 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
124 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
125 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
127 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
128 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
134 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
139 {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)}, /* GPIO0_18 */
144 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
145 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
146 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
147 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
148 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
149 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
150 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
151 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
152 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
153 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
154 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
155 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
156 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
157 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
162 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
163 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
164 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
165 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
166 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
167 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
168 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
169 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
170 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
171 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
172 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
173 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
174 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
175 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
176 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
181 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
182 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
183 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* MII1_CRS */
184 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
185 {OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
186 {OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
187 {OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
188 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
189 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
190 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
196 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
197 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
198 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
199 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
200 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
201 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
202 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
203 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
205 {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
206 {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
207 {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
208 {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
209 {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
210 {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
211 {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
212 {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
214 {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* nWAIT */
215 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* nWP */
216 {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* nCS */
217 {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* WEN */
218 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* OE */
219 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* ADV_ALE */
220 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */
225 {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* NOR_A0 */
226 {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* NOR_A1 */
227 {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* NOR_A2 */
228 {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* NOR_A3 */
229 {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* NOR_A4 */
230 {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* NOR_A5 */
231 {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* NOR_A6 */
232 {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* NOR_A7 */
233 {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD0 */
234 {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD1 */
235 {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD2 */
236 {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD3 */
237 {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD4 */
238 {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD5 */
239 {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD6 */
240 {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD7 */
241 {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD8 */
242 {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD9 */
243 {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD10 */
244 {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD11 */
245 {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD12 */
246 {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD13 */
247 {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD14 */
248 {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* NOR_AD15 */
249 {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */
250 {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */
251 {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */
252 {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */
253 {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */
254 {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/
260 {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
261 {OFFSET(mii1_rxd2), MODE(1) | PULLUDEN}, /* UART3_TXD */