40 	out_be32(&im->sysconf.ddrlaw[0].bar,  in fixed_sdram()
42 	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));  in fixed_sdram()
43 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);  in fixed_sdram()
54 	out_be32(&im->ddr.csbnds[0].csbnds,  in fixed_sdram()
58 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);  in fixed_sdram()
61 	out_be32(&im->ddr.cs_config[1], 0);  in fixed_sdram()
63 	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);  in fixed_sdram()
64 	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);  in fixed_sdram()
65 	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);  in fixed_sdram()
66 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);  in fixed_sdram()
67 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);  in fixed_sdram()
69 	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);  in fixed_sdram()
71 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);  in fixed_sdram()
72 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);  in fixed_sdram()
73 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);  in fixed_sdram()
75 	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);  in fixed_sdram()
103 	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);  in dram_init()
104 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);  in dram_init()
185 	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);  in pci_init_board()
186 	out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);  in pci_init_board()
188 	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);  in pci_init_board()
189 	out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);  in pci_init_board()