Lines Matching refs:post_div
45 unsigned int post_div; member
57 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) in ast2500_get_mpll_rate() local
60 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_mpll_rate()
72 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) in ast2500_get_hpll_rate() local
75 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_hpll_rate()
193 for (it.post_div = 0; it.post_div <= max_vals.post_div; in ast2500_calc_clock_config()
194 ++it.post_div) { in ast2500_calc_clock_config()
195 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) in ast2500_calc_clock_config()
202 / (it.post_div + 1); in ast2500_calc_clock_config()
227 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), in ast2500_configure_ddr()
235 mpll_reg |= (div_cfg.post_div << SCU_MPLL_POST_SHIFT) in ast2500_configure_ddr()
333 .post_div = SCU_D2PLL_POST_MASK >> SCU_D2PLL_POST_SHIFT, in ast2500_configure_d2pll()
355 | (div_cfg.post_div << SCU_D2PLL_POST_SHIFT), in ast2500_configure_d2pll()