78 static ulong ast2500_get_clkin(struct ast2500_scu *scu)  in ast2500_get_clkin()  argument
80 	return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ  in ast2500_get_clkin()
92 static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)  in ast2500_get_uart_clk_rate()  argument
103 	if (readl(&scu->misc_ctrl2) &  in ast2500_get_uart_clk_rate()
109 	if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13)  in ast2500_get_uart_clk_rate()
118 	ulong clkin = ast2500_get_clkin(priv->scu);  in ast2500_clk_get_rate()
129 					     readl(&priv->scu->h_pll_param));  in ast2500_clk_get_rate()
133 					     readl(&priv->scu->m_pll_param));  in ast2500_clk_get_rate()
137 			ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)  in ast2500_clk_get_rate()
142 							   scu->h_pll_param));  in ast2500_clk_get_rate()
147 		rate = ast2500_get_uart_clk_rate(priv->scu, 1);  in ast2500_clk_get_rate()
150 		rate = ast2500_get_uart_clk_rate(priv->scu, 2);  in ast2500_clk_get_rate()
153 		rate = ast2500_get_uart_clk_rate(priv->scu, 3);  in ast2500_clk_get_rate()
156 		rate = ast2500_get_uart_clk_rate(priv->scu, 4);  in ast2500_clk_get_rate()
159 		rate = ast2500_get_uart_clk_rate(priv->scu, 5);  in ast2500_clk_get_rate()
220 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)  in ast2500_configure_ddr()  argument
222 	ulong clkin = ast2500_get_clkin(scu);  in ast2500_configure_ddr()
232 	mpll_reg = readl(&scu->m_pll_param);  in ast2500_configure_ddr()
239 	ast_scu_unlock(scu);  in ast2500_configure_ddr()
240 	writel(mpll_reg, &scu->m_pll_param);  in ast2500_configure_ddr()
241 	ast_scu_lock(scu);  in ast2500_configure_ddr()
246 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index)  in ast2500_configure_mac()  argument
248 	ulong clkin = ast2500_get_clkin(scu);  in ast2500_configure_mac()
250 						readl(&scu->h_pll_param));  in ast2500_configure_mac()
261 	hwstrap = readl(&scu->hwstrap);  in ast2500_configure_mac()
292 	ast_scu_unlock(scu);  in ast2500_configure_mac()
293 	clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK,  in ast2500_configure_mac()
301 	setbits_le32(&scu->sysreset_ctrl1, reset_bit);  in ast2500_configure_mac()
303 	clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit);  in ast2500_configure_mac()
305 	clrbits_le32(&scu->sysreset_ctrl1, reset_bit);  in ast2500_configure_mac()
309 	       &scu->clk_duty_sel);  in ast2500_configure_mac()
311 	ast_scu_lock(scu);  in ast2500_configure_mac()
316 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)  in ast2500_configure_d2pll()  argument
335 	ulong clkin = ast2500_get_clkin(scu);  in ast2500_configure_d2pll()
338 	ast_scu_unlock(scu);  in ast2500_configure_d2pll()
341 	       | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]);  in ast2500_configure_d2pll()
347 	clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF,  in ast2500_configure_d2pll()
356 	       &scu->d2_pll_param);  in ast2500_configure_d2pll()
358 	clrbits_le32(&scu->d2_pll_ext_param[0],  in ast2500_configure_d2pll()
361 	clrsetbits_le32(&scu->misc_ctrl2,  in ast2500_configure_d2pll()
367 	writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay);  in ast2500_configure_d2pll()
368 	writel(clk_delay_settings, &scu->mac_clk_delay_100M);  in ast2500_configure_d2pll()
369 	writel(clk_delay_settings, &scu->mac_clk_delay_10M);  in ast2500_configure_d2pll()
371 	ast_scu_lock(scu);  in ast2500_configure_d2pll()
384 		new_rate = ast2500_configure_ddr(priv->scu, rate);  in ast2500_clk_set_rate()
387 		new_rate = ast2500_configure_d2pll(priv->scu, rate);  in ast2500_clk_set_rate()
407 		ast2500_configure_mac(priv->scu, 1);  in ast2500_clk_enable()
410 		ast2500_configure_mac(priv->scu, 2);  in ast2500_clk_enable()
413 		ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);  in ast2500_clk_enable()
431 	priv->scu = devfdt_get_addr_ptr(dev);  in ast2500_clk_probe()
432 	if (IS_ERR(priv->scu))  in ast2500_clk_probe()
433 		return PTR_ERR(priv->scu);  in ast2500_clk_probe()