137 	const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];  member
157 	const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];  member
184 	u32 idiv;  member
349 	val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;  in hsdk_pll_set_cfg()
373 	u32 idiv, fbdiv, odiv;  in pll_get()  local
389 	idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);  in pll_get()
396 	do_div(rate, idiv * odiv);  in pll_get()
562 		clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;  in axi_clk_set()
563 		hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);  in axi_clk_set()
600 		clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;  in tun_clk_set()
601 		hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);  in tun_clk_set()