Lines Matching refs:pll_get
272 static ulong pll_get(struct clk *);
285 { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
287 { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
288 { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
305 { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
309 { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
369 static ulong pll_get(struct clk *sclk) in pll_get() function
510 ulong parent_rate = pll_get(sclk); in idiv_get()
542 pll_rate = pll_get(sclk); in axi_clk_set()
580 pll_rate = pll_get(sclk); in tun_clk_set()
614 ulong parent_rate = pll_get(sclk); in idiv_set()