59 		return &slcr_base->arm_pll_ctrl;  in zynq_clk_get_register()
61 		return &slcr_base->ddr_pll_ctrl;  in zynq_clk_get_register()
63 		return &slcr_base->io_pll_ctrl;  in zynq_clk_get_register()
65 		return &slcr_base->lqspi_clk_ctrl;  in zynq_clk_get_register()
67 		return &slcr_base->smc_clk_ctrl;  in zynq_clk_get_register()
69 		return &slcr_base->pcap_clk_ctrl;  in zynq_clk_get_register()
71 		return &slcr_base->sdio_clk_ctrl;  in zynq_clk_get_register()
73 		return &slcr_base->uart_clk_ctrl;  in zynq_clk_get_register()
75 		return &slcr_base->spi_clk_ctrl;  in zynq_clk_get_register()
78 		return &slcr_base->dci_clk_ctrl;  in zynq_clk_get_register()
80 		return &slcr_base->gem0_clk_ctrl;  in zynq_clk_get_register()
82 		return &slcr_base->gem1_clk_ctrl;  in zynq_clk_get_register()
84 		return &slcr_base->fpga0_clk_ctrl;  in zynq_clk_get_register()
86 		return &slcr_base->fpga1_clk_ctrl;  in zynq_clk_get_register()
88 		return &slcr_base->fpga2_clk_ctrl;  in zynq_clk_get_register()
90 		return &slcr_base->fpga3_clk_ctrl;  in zynq_clk_get_register()
92 		return &slcr_base->can_clk_ctrl;  in zynq_clk_get_register()
97 		return &slcr_base->dbg_clk_ctrl;  in zynq_clk_get_register()
157 		clk_ctrl = readl(&slcr_base->gem0_rclk_ctrl);  in zynq_clk_get_gem_rclk()
159 		clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl);  in zynq_clk_get_gem_rclk()
174 	clk_ctrl = readl(&slcr_base->arm_clk_ctrl);  in zynq_clk_get_cpu_rate()
183 		clk_621 = readl(&slcr_base->clk_621_true) & 1;  in zynq_clk_get_cpu_rate()
205 	clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);  in zynq_clk_get_ddr2x_rate()
217 	clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);  in zynq_clk_get_ddr3x_rate()
229 	clk_ctrl = readl(&slcr_base->dci_clk_ctrl);  in zynq_clk_get_dci_rate()