62 	debug("workaround rows - memsize %lld\n", memsize);  in get_errata_rows()
63 	debug("workaround rows - cs        %d\n", cs);  in get_errata_rows()
64 	debug("workaround rows - width     %d\n", width);  in get_errata_rows()
65 	debug("workaround rows - rows      %d\n", rows);  in get_errata_rows()
66 	debug("workaround rows - banks     %d\n", banks);  in get_errata_rows()
67 	debug("workaround rows - cols      %d\n", cols);  in get_errata_rows()
70 	debug("rows workaround - term1 %lld\n", newrows);  in get_errata_rows()
73 	debug("rows workaround - term2 %lld\n", newrows);  in get_errata_rows()
82 	debug("rows workaround - bits %d\n", bits);  in get_errata_rows()
96 	debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);  in get_errata_rows()
120 	debug("sdram set rule start %x, %d\n", lo_addr_bits,  in sdram_set_rule()
122 	debug("sdram set rule end   %x, %d\n", hi_addr_bits,  in sdram_set_rule()
214 	debug("SDRAM Prot rule, default %x\n",  in sdram_dump_protection_config()
220 		debug("Rule %d, rules ...\n", rules);  in sdram_dump_protection_config()
221 		debug("    sdram start %x\n", rule.sdram_start);  in sdram_dump_protection_config()
222 		debug("    sdram end   %x\n", rule.sdram_end);  in sdram_dump_protection_config()
223 		debug("    low prot id %d, hi prot id %d\n",  in sdram_dump_protection_config()
226 		debug("    portmask %x\n", rule.portmask);  in sdram_dump_protection_config()
227 		debug("    security %d\n", rule.security);  in sdram_dump_protection_config()
228 		debug("    result %d\n", rule.result);  in sdram_dump_protection_config()
229 		debug("    valid %d\n", rule.valid);  in sdram_dump_protection_config()
245 	debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);  in sdram_write_verify()
248 	debug("   Read and verify...");  in sdram_write_verify()
251 		debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",  in sdram_write_verify()
256 	debug("correct!\n");  in sdram_write_verify()
284 			debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");  in sdr_get_ctrlcfg()
288 			debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");  in sdr_get_ctrlcfg()
330 	debug("\nConfiguring CTRLCFG\n");  in sdr_load_regs()
333 	debug("Configuring DRAMTIMING1\n");  in sdr_load_regs()
336 	debug("Configuring DRAMTIMING2\n");  in sdr_load_regs()
339 	debug("Configuring DRAMTIMING3\n");  in sdr_load_regs()
342 	debug("Configuring DRAMTIMING4\n");  in sdr_load_regs()
345 	debug("Configuring LOWPWRTIMING\n");  in sdr_load_regs()
348 	debug("Configuring DRAMADDRW\n");  in sdr_load_regs()
351 	debug("Configuring DRAMIFWIDTH\n");  in sdr_load_regs()
354 	debug("Configuring DRAMDEVWIDTH\n");  in sdr_load_regs()
357 	debug("Configuring LOWPWREQ\n");  in sdr_load_regs()
360 	debug("Configuring DRAMINTR\n");  in sdr_load_regs()
363 	debug("Configuring STATICCFG\n");  in sdr_load_regs()
366 	debug("Configuring CTRLWIDTH\n");  in sdr_load_regs()
369 	debug("Configuring PORTCFG\n");  in sdr_load_regs()
372 	debug("Configuring FIFOCFG\n");  in sdr_load_regs()
375 	debug("Configuring MPPRIORITY\n");  in sdr_load_regs()
378 	debug("Configuring MPWEIGHT_MPWEIGHT_0\n");  in sdr_load_regs()
384 	debug("Configuring MPPACING_MPPACING_0\n");  in sdr_load_regs()
390 	debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");  in sdr_load_regs()
395 	debug("Configuring PHYCTRL_PHYCTRL_0\n");  in sdr_load_regs()
398 	debug("Configuring CPORTWIDTH\n");  in sdr_load_regs()
401 	debug("Configuring CPORTWMAP\n");  in sdr_load_regs()
404 	debug("Configuring CPORTRMAP\n");  in sdr_load_regs()
407 	debug("Configuring RFIFOCMAP\n");  in sdr_load_regs()
410 	debug("Configuring WFIFOCMAP\n");  in sdr_load_regs()
413 	debug("Configuring CPORTRDWR\n");  in sdr_load_regs()
416 	debug("Configuring DRAMODT\n");  in sdr_load_regs()
419 	debug("Configuring EXTRATIME1\n");  in sdr_load_regs()
457 	debug("Configuring STATICCFG\n");  in sdram_mmr_init_full()
533 	debug("%s returns %ld\n", __func__, temp);  in sdram_calculate_size()