Lines Matching refs:rwcfg
33 const struct socfpga_sdram_rw_mgr_config *rwcfg; variable
138 ratio = rwcfg->mem_dq_per_read_dqs / in phy_mgr_initialize()
139 rwcfg->mem_virtual_groups_per_read_dqs; in phy_mgr_initialize()
142 param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1; in phy_mgr_initialize()
143 param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1; in phy_mgr_initialize()
163 switch (rwcfg->mem_number_of_ranks) { in set_rank_and_odt_mask()
170 if (rwcfg->mem_number_of_cs_per_dimm == 1) { in set_rank_and_odt_mask()
312 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, in scc_mgr_set_dqs_io_in_delay()
319 rwcfg->mem_dq_per_write_dqs + 1 + dm, in scc_mgr_set_dm_in_delay()
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs, in scc_mgr_set_dqs_out1_delay()
337 rwcfg->mem_dq_per_write_dqs + 1 + dm, in scc_mgr_set_dm_out1_delay()
380 for (r = 0; r < rwcfg->mem_number_of_ranks; in scc_mgr_set_all_ranks()
444 const int ratio = rwcfg->mem_if_read_dqs_width / in scc_mgr_set_oct_out1_delay()
445 rwcfg->mem_if_write_dqs_width; in scc_mgr_set_oct_out1_delay()
501 for (r = 0; r < rwcfg->mem_number_of_ranks; in scc_mgr_zero_all()
503 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { in scc_mgr_zero_all()
514 for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { in scc_mgr_zero_all()
556 const int ratio = rwcfg->mem_if_read_dqs_width / in scc_mgr_load_dqs_for_write_group()
557 rwcfg->mem_if_write_dqs_width; in scc_mgr_load_dqs_for_write_group()
580 for (r = 0; r < rwcfg->mem_number_of_ranks; in scc_mgr_zero_group()
583 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { in scc_mgr_zero_group()
627 for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) { in scc_mgr_apply_group_dq_in_delay()
643 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { in scc_mgr_apply_group_dq_out1_delay()
685 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) in scc_mgr_apply_group_all_out_delay_add()
734 for (r = 0; r < rwcfg->mem_number_of_ranks; in scc_mgr_apply_group_all_out_delay_add_all_ranks()
755 writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0); in set_jump_as_return()
810 writel(rwcfg->idle_loop1, in delay_for_n_mem_clocks()
813 writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS | in delay_for_n_mem_clocks()
822 writel(rwcfg->idle_loop2, in delay_for_n_mem_clocks()
825 writel(rwcfg->idle_loop2, in delay_for_n_mem_clocks()
829 writel(rwcfg->idle_loop2, in delay_for_n_mem_clocks()
883 for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { in rw_mgr_mem_load_user()
889 writel(rwcfg->precharge_all, grpaddr); in rw_mgr_mem_load_user()
895 if ((rwcfg->mem_address_mirroring >> r) & 0x1) { in rw_mgr_mem_load_user()
897 writel(rwcfg->mrs2_mirr, grpaddr); in rw_mgr_mem_load_user()
900 writel(rwcfg->mrs3_mirr, grpaddr); in rw_mgr_mem_load_user()
903 writel(rwcfg->mrs1_mirr, grpaddr); in rw_mgr_mem_load_user()
909 writel(rwcfg->mrs2, grpaddr); in rw_mgr_mem_load_user()
912 writel(rwcfg->mrs3, grpaddr); in rw_mgr_mem_load_user()
915 writel(rwcfg->mrs1, grpaddr); in rw_mgr_mem_load_user()
924 writel(rwcfg->zqcl, grpaddr); in rw_mgr_mem_load_user()
970 rwcfg->init_reset_0_cke_0); in rw_mgr_mem_initialize()
992 rwcfg->init_reset_1_cke_0); in rw_mgr_mem_initialize()
999 rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset, in rw_mgr_mem_initialize()
1011 rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1); in rw_mgr_mem_handoff()
1075 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1; in rw_mgr_mem_calibrate_write_test_issue()
1076 writel(rwcfg->lfsr_wr_rd_dm_bank_0_data, in rw_mgr_mem_calibrate_write_test_issue()
1078 writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, in rw_mgr_mem_calibrate_write_test_issue()
1081 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1; in rw_mgr_mem_calibrate_write_test_issue()
1082 writel(rwcfg->lfsr_wr_rd_bank_0_data, in rw_mgr_mem_calibrate_write_test_issue()
1084 writel(rwcfg->lfsr_wr_rd_bank_0_nop, in rw_mgr_mem_calibrate_write_test_issue()
1097 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; in rw_mgr_mem_calibrate_write_test_issue()
1098 writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs, in rw_mgr_mem_calibrate_write_test_issue()
1101 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; in rw_mgr_mem_calibrate_write_test_issue()
1102 writel(rwcfg->lfsr_wr_rd_bank_0_dqs, in rw_mgr_mem_calibrate_write_test_issue()
1120 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0; in rw_mgr_mem_calibrate_write_test_issue()
1121 writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop, in rw_mgr_mem_calibrate_write_test_issue()
1124 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0; in rw_mgr_mem_calibrate_write_test_issue()
1125 writel(rwcfg->lfsr_wr_rd_bank_0_nop, in rw_mgr_mem_calibrate_write_test_issue()
1147 writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait, in rw_mgr_mem_calibrate_write_test_issue()
1150 writel(rwcfg->lfsr_wr_rd_bank_0_wait, in rw_mgr_mem_calibrate_write_test_issue()
1176 rwcfg->mem_number_of_ranks : in rw_mgr_mem_calibrate_write_test()
1178 const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs / in rw_mgr_mem_calibrate_write_test()
1179 rwcfg->mem_virtual_groups_per_write_dqs; in rw_mgr_mem_calibrate_write_test()
1192 for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1; in rw_mgr_mem_calibrate_write_test()
1199 rwcfg->mem_virtual_groups_per_write_dqs + vg, in rw_mgr_mem_calibrate_write_test()
1242 (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2; in rw_mgr_mem_calibrate_read_test_patterns()
1244 rwcfg->mem_number_of_ranks : in rw_mgr_mem_calibrate_read_test_patterns()
1246 const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs / in rw_mgr_mem_calibrate_read_test_patterns()
1247 rwcfg->mem_virtual_groups_per_read_dqs; in rw_mgr_mem_calibrate_read_test_patterns()
1262 writel(rwcfg->guaranteed_read, in rw_mgr_mem_calibrate_read_test_patterns()
1266 writel(rwcfg->guaranteed_read_cont, in rw_mgr_mem_calibrate_read_test_patterns()
1270 for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; in rw_mgr_mem_calibrate_read_test_patterns()
1276 writel(rwcfg->guaranteed_read, in rw_mgr_mem_calibrate_read_test_patterns()
1287 writel(rwcfg->clear_dqs_enable, addr + (group << 2)); in rw_mgr_mem_calibrate_read_test_patterns()
1313 rwcfg->mem_number_of_ranks : in rw_mgr_mem_calibrate_read_load_patterns()
1326 writel(rwcfg->guaranteed_write_wait0, in rw_mgr_mem_calibrate_read_load_patterns()
1331 writel(rwcfg->guaranteed_write_wait1, in rw_mgr_mem_calibrate_read_load_patterns()
1336 writel(rwcfg->guaranteed_write_wait2, in rw_mgr_mem_calibrate_read_load_patterns()
1341 writel(rwcfg->guaranteed_write_wait3, in rw_mgr_mem_calibrate_read_load_patterns()
1344 writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_read_load_patterns()
1371 const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks : in rw_mgr_mem_calibrate_read_test()
1391 writel(rwcfg->read_b2b_wait1, in rw_mgr_mem_calibrate_read_test()
1395 writel(rwcfg->read_b2b_wait2, in rw_mgr_mem_calibrate_read_test()
1406 writel(rwcfg->read_b2b, in rw_mgr_mem_calibrate_read_test()
1409 writel(rwcfg->mem_if_read_dqs_width * in rw_mgr_mem_calibrate_read_test()
1410 rwcfg->mem_virtual_groups_per_read_dqs - 1, in rw_mgr_mem_calibrate_read_test()
1415 writel(rwcfg->read_b2b, in rw_mgr_mem_calibrate_read_test()
1419 for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0; in rw_mgr_mem_calibrate_read_test()
1434 writel(rwcfg->read_b2b, addr + in rw_mgr_mem_calibrate_read_test()
1436 rwcfg->mem_virtual_groups_per_read_dqs + in rw_mgr_mem_calibrate_read_test()
1440 tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs / in rw_mgr_mem_calibrate_read_test()
1441 rwcfg->mem_virtual_groups_per_read_dqs; in rw_mgr_mem_calibrate_read_test()
1449 writel(rwcfg->clear_dqs_enable, addr + (group << 2)); in rw_mgr_mem_calibrate_read_test()
1981 const u32 ratio = rwcfg->mem_if_read_dqs_width / in search_stop_check()
1982 rwcfg->mem_if_write_dqs_width; in search_stop_check()
1985 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in search_stop_check()
1986 rwcfg->mem_dq_per_read_dqs; in search_stop_check()
2040 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in search_left_edge()
2041 rwcfg->mem_dq_per_read_dqs; in search_left_edge()
2151 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in search_right_edge()
2152 rwcfg->mem_dq_per_read_dqs; in search_right_edge()
2178 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; in search_right_edge()
2269 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in get_window_mid_index()
2270 rwcfg->mem_dq_per_read_dqs; in get_window_mid_index()
2320 const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs : in center_dq_windows()
2321 rwcfg->mem_dq_per_read_dqs; in center_dq_windows()
2400 int32_t left_edge[rwcfg->mem_dq_per_read_dqs]; in rw_mgr_mem_calibrate_vfifo_center()
2401 int32_t right_edge[rwcfg->mem_dq_per_read_dqs]; in rw_mgr_mem_calibrate_vfifo_center()
2417 for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) { in rw_mgr_mem_calibrate_vfifo_center()
2451 rwcfg->mem_dq_per_read_dqs + i, in rw_mgr_mem_calibrate_vfifo_center()
2456 rwcfg->mem_dq_per_read_dqs + i, in rw_mgr_mem_calibrate_vfifo_center()
2582 (rwcfg->mem_dq_per_read_dqs - 1); in rw_mgr_mem_calibrate_dqs_enable_calibration()
2589 for (r = 0; r < rwcfg->mem_number_of_ranks; in rw_mgr_mem_calibrate_dqs_enable_calibration()
2592 i < rwcfg->mem_dq_per_read_dqs; in rw_mgr_mem_calibrate_dqs_enable_calibration()
2615 for (r = 0; r < rwcfg->mem_number_of_ranks; in rw_mgr_mem_calibrate_dqs_enable_calibration()
2649 rank_bgn < rwcfg->mem_number_of_ranks; in rw_mgr_mem_calibrate_dq_dqs_centering()
2953 int left_edge[rwcfg->mem_dq_per_write_dqs]; in rw_mgr_mem_calibrate_writes_center()
2954 int right_edge[rwcfg->mem_dq_per_write_dqs]; in rw_mgr_mem_calibrate_writes_center()
2973 (rwcfg->mem_dq_per_write_dqs << 2)); in rw_mgr_mem_calibrate_writes_center()
2982 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) { in rw_mgr_mem_calibrate_writes_center()
3143 for (r = 0; r < rwcfg->mem_number_of_ranks; r++) { in mem_precharge_and_activate()
3148 writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS | in mem_precharge_and_activate()
3152 writel(rwcfg->activate_0_and_1_wait1, in mem_precharge_and_activate()
3156 writel(rwcfg->activate_0_and_1_wait2, in mem_precharge_and_activate()
3160 writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS | in mem_precharge_and_activate()
3217 for (r = 0; r < rwcfg->mem_number_of_ranks; in mem_skip_calibrate()
3223 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { in mem_skip_calibrate()
3261 for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) { in mem_skip_calibrate()
3271 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { in mem_skip_calibrate()
3309 const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width / in mem_calibrate()
3310 rwcfg->mem_if_write_dqs_width; in mem_calibrate()
3327 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) { in mem_calibrate()
3364 < rwcfg->mem_if_write_dqs_width; write_group++, in mem_calibrate()
3365 write_test_bgn += rwcfg->mem_dq_per_write_dqs) { in mem_calibrate()
3385 read_test_bgn += rwcfg->mem_dq_per_read_dqs) { in mem_calibrate()
3404 rank_bgn < rwcfg->mem_number_of_ranks; in mem_calibrate()
3434 read_test_bgn += rwcfg->mem_dq_per_read_dqs) { in mem_calibrate()
3696 writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) | in initialize_tracking()
3697 (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0), in initialize_tracking()
3700 writel(rwcfg->mem_if_read_dqs_width, in initialize_tracking()
3704 writel((rwcfg->refresh_all << 24) | (1000 << 0), in initialize_tracking()
3720 rwcfg = socfpga_get_sdram_rwmgr_config(); in sdram_calibration_full()
3748 rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm, in sdram_calibration_full()
3749 rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs, in sdram_calibration_full()
3750 rwcfg->mem_virtual_groups_per_read_dqs, in sdram_calibration_full()
3751 rwcfg->mem_virtual_groups_per_write_dqs); in sdram_calibration_full()
3754 rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width, in sdram_calibration_full()
3755 rwcfg->mem_data_width, rwcfg->mem_data_mask_width, in sdram_calibration_full()