18 static struct socfpga_sdr_reg_file *sdr_reg_file =  variable
94 	clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);  in reg_file_set_group()
99 	clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);  in reg_file_set_stage()
105 	clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);  in reg_file_set_sub_stage()
1953 	writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);  in rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
3550 		writel(debug_info, &sdr_reg_file->fom);  in debug_mem_calibrate()
3561 		writel(debug_info, &sdr_reg_file->failing_stage);  in debug_mem_calibrate()
3569 		writel(debug_info, &sdr_reg_file->failing_stage);  in debug_mem_calibrate()
3605 	writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature);  in initialize_reg_file()
3606 	writel(0, &sdr_reg_file->debug_data_addr);  in initialize_reg_file()
3607 	writel(0, &sdr_reg_file->cur_stage);  in initialize_reg_file()
3608 	writel(0, &sdr_reg_file->fom);  in initialize_reg_file()
3609 	writel(0, &sdr_reg_file->failing_stage);  in initialize_reg_file()
3610 	writel(0, &sdr_reg_file->debug1);  in initialize_reg_file()
3611 	writel(0, &sdr_reg_file->debug2);  in initialize_reg_file()
3678 	       &sdr_reg_file->dtaps_per_ptap);  in initialize_tracking()
3681 	writel(7500, &sdr_reg_file->trk_sample_count);  in initialize_tracking()
3684 	writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);  in initialize_tracking()
3693 	       &sdr_reg_file->delays);  in initialize_tracking()
3698 	       &sdr_reg_file->trk_rw_mgr_addr);  in initialize_tracking()
3701 	       &sdr_reg_file->trk_read_dqs_width);  in initialize_tracking()
3705 	       &sdr_reg_file->trk_rfsh);  in initialize_tracking()