34 	struct ccsr_ddr __iomem *ddr;  in fsl_ddr_set_memctl_regs()  local
41 		ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;  in fsl_ddr_set_memctl_regs()
45 		ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;  in fsl_ddr_set_memctl_regs()
50 		ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;  in fsl_ddr_set_memctl_regs()
55 		ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;  in fsl_ddr_set_memctl_regs()
67 		ddr_out32(&ddr->eor, regs->ddr_eor);  in fsl_ddr_set_memctl_regs()
70 			ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
71 			ddr_out32(&ddr->cs0_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
72 			ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
75 			ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
76 			ddr_out32(&ddr->cs1_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
77 			ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
80 			ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
81 			ddr_out32(&ddr->cs2_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
82 			ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
85 			ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
86 			ddr_out32(&ddr->cs3_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
87 			ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
91 	ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);  in fsl_ddr_set_memctl_regs()
92 	ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);  in fsl_ddr_set_memctl_regs()
93 	ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);  in fsl_ddr_set_memctl_regs()
94 	ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);  in fsl_ddr_set_memctl_regs()
95 	ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);  in fsl_ddr_set_memctl_regs()
96 	ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);  in fsl_ddr_set_memctl_regs()
97 	ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);  in fsl_ddr_set_memctl_regs()
98 	ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);  in fsl_ddr_set_memctl_regs()
99 	ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);  in fsl_ddr_set_memctl_regs()
100 	ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);  in fsl_ddr_set_memctl_regs()
101 	ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);  in fsl_ddr_set_memctl_regs()
102 	ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);  in fsl_ddr_set_memctl_regs()
103 	ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);  in fsl_ddr_set_memctl_regs()
104 	ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);  in fsl_ddr_set_memctl_regs()
105 	ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);  in fsl_ddr_set_memctl_regs()
106 	ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);  in fsl_ddr_set_memctl_regs()
107 	ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);  in fsl_ddr_set_memctl_regs()
108 	ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);  in fsl_ddr_set_memctl_regs()
109 	ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);  in fsl_ddr_set_memctl_regs()
110 	ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);  in fsl_ddr_set_memctl_regs()
118 		ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);  in fsl_ddr_set_memctl_regs()
120 		ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);  in fsl_ddr_set_memctl_regs()
123 	ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);  in fsl_ddr_set_memctl_regs()
124 	ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);  in fsl_ddr_set_memctl_regs()
125 	ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);  in fsl_ddr_set_memctl_regs()
126 	ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);  in fsl_ddr_set_memctl_regs()
129 		ddr_out32(&ddr->sdram_cfg_2,  in fsl_ddr_set_memctl_regs()
131 		ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);  in fsl_ddr_set_memctl_regs()
132 		ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);  in fsl_ddr_set_memctl_regs()
135 		ddr_out32(&ddr->ddr_cdr2,  in fsl_ddr_set_memctl_regs()
140 		ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);  in fsl_ddr_set_memctl_regs()
141 		ddr_out32(&ddr->init_addr, regs->ddr_init_addr);  in fsl_ddr_set_memctl_regs()
142 		ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);  in fsl_ddr_set_memctl_regs()
143 		ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);  in fsl_ddr_set_memctl_regs()
145 	ddr_out32(&ddr->err_disable, regs->err_disable);  in fsl_ddr_set_memctl_regs()
146 	ddr_out32(&ddr->err_int_en, regs->err_int_en);  in fsl_ddr_set_memctl_regs()
151 			ddr_out32(&ddr->debug[i], regs->debug[i]);  in fsl_ddr_set_memctl_regs()
172 	ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);  in fsl_ddr_set_memctl_regs()
186 		temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);  in fsl_ddr_set_memctl_regs()
188 		ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);  in fsl_ddr_set_memctl_regs()
192 		temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);  in fsl_ddr_set_memctl_regs()
195 		temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;  in fsl_ddr_set_memctl_regs()
197 	ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);  in fsl_ddr_set_memctl_regs()
222 	bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)  in fsl_ddr_set_memctl_regs()
231 	while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&  in fsl_ddr_set_memctl_regs()
242 		temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);  in fsl_ddr_set_memctl_regs()
244 		ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);  in fsl_ddr_set_memctl_regs()