Lines Matching refs:ctrl_num
84 const unsigned int ctrl_num) in compute_cas_write_latency() argument
87 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in compute_cas_write_latency()
118 const unsigned int ctrl_num) in compute_cas_write_latency() argument
121 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in compute_cas_write_latency()
294 static void set_timing_cfg_0(const unsigned int ctrl_num, in set_timing_cfg_0() argument
314 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in set_timing_cfg_0()
320 unsigned int data_rate = get_ddr_freq(ctrl_num); in set_timing_cfg_0()
342 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); in set_timing_cfg_0()
348 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000)); in set_timing_cfg_0()
350 unsigned int data_rate = get_ddr_freq(ctrl_num); in set_timing_cfg_0()
365 ip_rev = fsl_ddr_get_version(ctrl_num); in set_timing_cfg_0()
373 picos_to_mclk(ctrl_num, 15000)); in set_timing_cfg_0()
417 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); in set_timing_cfg_0()
453 static void set_timing_cfg_3(const unsigned int ctrl_num, in set_timing_cfg_3() argument
477 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4; in set_timing_cfg_3()
478 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4; in set_timing_cfg_3()
479 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4; in set_timing_cfg_3()
483 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4; in set_timing_cfg_3()
485 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4; in set_timing_cfg_3()
488 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) + in set_timing_cfg_3()
505 static void set_timing_cfg_1(const unsigned int ctrl_num, in set_timing_cfg_1() argument
541 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps); in set_timing_cfg_1()
542 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps); in set_timing_cfg_1()
543 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps); in set_timing_cfg_1()
571 if (fsl_ddr_get_version(ctrl_num) <= 0x40400) in set_timing_cfg_1()
578 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8; in set_timing_cfg_1()
579 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_timing_cfg_1()
580 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U); in set_timing_cfg_1()
581 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500)); in set_timing_cfg_1()
587 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8; in set_timing_cfg_1()
588 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_timing_cfg_1()
589 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps); in set_timing_cfg_1()
590 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps); in set_timing_cfg_1()
633 static void set_timing_cfg_2(const unsigned int ctrl_num, in set_timing_cfg_2() argument
655 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in set_timing_cfg_2()
673 wr_lat = compute_cas_write_latency(ctrl_num); in set_timing_cfg_2()
677 rd_to_pre = picos_to_mclk(ctrl_num, 7500); in set_timing_cfg_2()
679 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps); in set_timing_cfg_2()
697 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000)); in set_timing_cfg_2()
704 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 : in set_timing_cfg_2()
709 four_act = picos_to_mclk(ctrl_num, in set_timing_cfg_2()
726 static void set_ddr_sdram_rcw(const unsigned int ctrl_num, in set_ddr_sdram_rcw() argument
731 unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000; in set_ddr_sdram_rcw()
872 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, in set_ddr_sdram_cfg_2() argument
920 slow = get_ddr_freq(ctrl_num) < 1249000000; in set_ddr_sdram_cfg_2()
974 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, in set_ddr_sdram_mode_2() argument
986 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9; in set_ddr_sdram_mode_2()
989 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in set_ddr_sdram_mode_2()
1062 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, in set_ddr_sdram_mode_2() argument
1074 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5; in set_ddr_sdram_mode_2()
1138 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, in set_ddr_sdram_mode_2() argument
1269 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, in set_ddr_sdram_mode_10() argument
1278 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); in set_ddr_sdram_mode_10()
1325 static void set_ddr_sdram_interval(const unsigned int ctrl_num, in set_ddr_sdram_interval() argument
1333 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps); in set_ddr_sdram_interval()
1347 static void set_ddr_sdram_mode(const unsigned int ctrl_num, in set_ddr_sdram_mode() argument
1423 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1518 static void set_ddr_sdram_mode(const unsigned int ctrl_num, in set_ddr_sdram_mode() argument
1598 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1714 static void set_ddr_sdram_mode(const unsigned int ctrl_num, in set_ddr_sdram_mode() argument
1787 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1995 static void set_timing_cfg_7(const unsigned int ctrl_num, in set_timing_cfg_7() argument
2002 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in set_timing_cfg_7()
2004 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); in set_timing_cfg_7()
2005 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); in set_timing_cfg_7()
2006 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); in set_timing_cfg_7()
2046 static void set_timing_cfg_8(const unsigned int ctrl_num, in set_timing_cfg_8() argument
2054 int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); in set_timing_cfg_8()
2078 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps); in set_timing_cfg_8()
2079 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500)); in set_timing_cfg_8()
2098 static void set_timing_cfg_9(const unsigned int ctrl_num, in set_timing_cfg_9() argument
2108 picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps); in set_timing_cfg_9()
2347 compute_fsl_memctl_config_regs(const unsigned int ctrl_num, in compute_fsl_memctl_config_regs() argument
2372 switch (ctrl_num) { in compute_fsl_memctl_config_regs()
2392 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); in compute_fsl_memctl_config_regs()
2552 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); in compute_fsl_memctl_config_regs()
2555 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, in compute_fsl_memctl_config_regs()
2557 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2558 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2564 ip_rev = fsl_ddr_get_version(ctrl_num); in compute_fsl_memctl_config_regs()
2571 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); in compute_fsl_memctl_config_regs()
2572 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2574 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2577 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2579 set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2581 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2591 set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2592 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2593 set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2630 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; in compute_fsl_memctl_config_regs()