Lines Matching refs:ddr
148 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, in set_csn_config() argument
225 ddr->cs[i].config = (0 in set_csn_config()
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
249 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) in set_csn_config_2() argument
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
295 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_0() argument
438 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
448 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in set_timing_cfg_0()
454 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_3() argument
491 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
501 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); in set_timing_cfg_3()
506 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_1() argument
619 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
629 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); in set_timing_cfg_1()
634 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_2() argument
712 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
722 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); in set_timing_cfg_2()
727 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_rcw() argument
737 ddr->ddr_sdram_rcw_1 = popts->rcw_1; in set_ddr_sdram_rcw()
738 ddr->ddr_sdram_rcw_2 = popts->rcw_2; in set_ddr_sdram_rcw()
739 ddr->ddr_sdram_rcw_3 = popts->rcw_3; in set_ddr_sdram_rcw()
751 ddr->ddr_sdram_rcw_1 = in set_ddr_sdram_rcw()
760 ddr->ddr_sdram_rcw_2 = in set_ddr_sdram_rcw()
769 ddr->ddr_sdram_rcw_3 = in set_ddr_sdram_rcw()
773 ddr->ddr_sdram_rcw_1); in set_ddr_sdram_rcw()
775 ddr->ddr_sdram_rcw_2); in set_ddr_sdram_rcw()
777 ddr->ddr_sdram_rcw_3); in set_ddr_sdram_rcw()
782 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg() argument
848 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
868 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); in set_ddr_sdram_cfg()
873 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg_2() argument
939 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; in set_ddr_sdram_cfg_2()
940 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); in set_ddr_sdram_cfg_2()
950 ddr->ddr_sdram_cfg_2 = (0 in set_ddr_sdram_cfg_2()
969 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); in set_ddr_sdram_cfg_2()
975 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
1016 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1020 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1033 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1039 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1045 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1053 ddr->ddr_sdram_mode_4); in set_ddr_sdram_mode_2()
1055 ddr->ddr_sdram_mode_6); in set_ddr_sdram_mode_2()
1057 ddr->ddr_sdram_mode_8); in set_ddr_sdram_mode_2()
1063 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
1091 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1095 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1108 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1114 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1120 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1128 ddr->ddr_sdram_mode_4); in set_ddr_sdram_mode_2()
1130 ddr->ddr_sdram_mode_6); in set_ddr_sdram_mode_2()
1132 ddr->ddr_sdram_mode_8); in set_ddr_sdram_mode_2()
1139 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
1147 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1151 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1157 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_9() argument
1170 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1171 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1172 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1173 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN)) in set_ddr_sdram_mode_9()
1176 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { in set_ddr_sdram_mode_9()
1188 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && in set_ddr_sdram_mode_9()
1202 ddr->ddr_sdram_mode_9 = (0 in set_ddr_sdram_mode_9()
1212 debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9); in set_ddr_sdram_mode_9()
1216 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) { in set_ddr_sdram_mode_9()
1223 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && in set_ddr_sdram_mode_9()
1240 ddr->ddr_sdram_mode_11 = (0 in set_ddr_sdram_mode_9()
1246 ddr->ddr_sdram_mode_13 = (0 in set_ddr_sdram_mode_9()
1252 ddr->ddr_sdram_mode_15 = (0 in set_ddr_sdram_mode_9()
1260 ddr->ddr_sdram_mode_11); in set_ddr_sdram_mode_9()
1262 ddr->ddr_sdram_mode_13); in set_ddr_sdram_mode_9()
1264 ddr->ddr_sdram_mode_15); in set_ddr_sdram_mode_9()
1270 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_10() argument
1285 ddr->ddr_sdram_mode_10 = (0 in set_ddr_sdram_mode_10()
1289 debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10); in set_ddr_sdram_mode_10()
1294 ddr->ddr_sdram_mode_12 = (0 in set_ddr_sdram_mode_10()
1300 ddr->ddr_sdram_mode_14 = (0 in set_ddr_sdram_mode_10()
1306 ddr->ddr_sdram_mode_16 = (0 in set_ddr_sdram_mode_10()
1314 ddr->ddr_sdram_mode_12); in set_ddr_sdram_mode_10()
1316 ddr->ddr_sdram_mode_14); in set_ddr_sdram_mode_10()
1318 ddr->ddr_sdram_mode_16); in set_ddr_sdram_mode_10()
1326 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_interval() argument
1338 ddr->ddr_sdram_interval = (0 in set_ddr_sdram_interval()
1342 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); in set_ddr_sdram_interval()
1348 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1470 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1475 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1488 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1494 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1500 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1508 ddr->ddr_sdram_mode_3); in set_ddr_sdram_mode()
1510 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1512 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1519 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1661 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1666 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1683 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1689 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1695 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1703 ddr->ddr_sdram_mode_3); in set_ddr_sdram_mode()
1705 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1707 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1715 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1835 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1839 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1844 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) in set_ddr_data_init() argument
1853 ddr->ddr_data_init = init_value; in set_ddr_data_init()
1861 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_clk_cntl() argument
1879 ddr->ddr_sdram_clk_cntl = (0 in set_ddr_sdram_clk_cntl()
1883 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); in set_ddr_sdram_clk_cntl()
1887 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) in set_ddr_init_addr() argument
1891 ddr->ddr_init_addr = init_addr; in set_ddr_init_addr()
1895 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) in set_ddr_init_ext_addr() argument
1900 ddr->ddr_init_ext_addr = (0 in set_ddr_init_ext_addr()
1907 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_4() argument
1937 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1945 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); in set_timing_cfg_4()
1949 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) in set_timing_cfg_5() argument
1957 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_5()
1958 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_5()
1967 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1973 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); in set_timing_cfg_5()
1977 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) in set_timing_cfg_6() argument
1985 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
1992 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); in set_timing_cfg_6()
1996 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_7() argument
2008 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN && in set_timing_cfg_7()
2011 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1; in set_timing_cfg_7()
2036 ddr->timing_cfg_7 = (0 in set_timing_cfg_7()
2043 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); in set_timing_cfg_7()
2047 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_8() argument
2055 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_8()
2056 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_8()
2085 ddr->timing_cfg_8 = (0 in set_timing_cfg_8()
2095 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); in set_timing_cfg_8()
2099 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_9() argument
2112 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 | in set_timing_cfg_9()
2115 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); in set_timing_cfg_9()
2119 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, in set_ddr_dq_mapping() argument
2122 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; in set_ddr_dq_mapping()
2134 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) | in set_ddr_dq_mapping()
2140 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) | in set_ddr_dq_mapping()
2146 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) | in set_ddr_dq_mapping()
2153 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) | in set_ddr_dq_mapping()
2159 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); in set_ddr_dq_mapping()
2160 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); in set_ddr_dq_mapping()
2161 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); in set_ddr_dq_mapping()
2162 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); in set_ddr_dq_mapping()
2164 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg_3() argument
2171 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; in set_ddr_sdram_cfg_3()
2173 ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0; in set_ddr_sdram_cfg_3()
2180 ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1) in set_ddr_sdram_cfg_3()
2185 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); in set_ddr_sdram_cfg_3()
2190 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) in set_ddr_zq_cntl() argument
2214 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
2223 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); in set_ddr_zq_cntl()
2227 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, in set_ddr_wrlvl_cntl() argument
2283 ddr->ddr_wrlvl_cntl = (0 in set_ddr_wrlvl_cntl()
2292 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); in set_ddr_wrlvl_cntl()
2293 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; in set_ddr_wrlvl_cntl()
2294 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); in set_ddr_wrlvl_cntl()
2295 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; in set_ddr_wrlvl_cntl()
2296 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); in set_ddr_wrlvl_cntl()
2301 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) in set_ddr_sr_cntr() argument
2304 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; in set_ddr_sr_cntr()
2307 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_eor() argument
2310 ddr->ddr_eor = 0x40000000; /* address hash enable */ in set_ddr_eor()
2315 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_cdr1() argument
2317 ddr->ddr_cdr1 = popts->ddr_cdr1; in set_ddr_cdr1()
2318 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); in set_ddr_cdr1()
2321 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_cdr2() argument
2323 ddr->ddr_cdr2 = popts->ddr_cdr2; in set_ddr_cdr2()
2324 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); in set_ddr_cdr2()
2328 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) in check_fsl_memctl_config_regs() argument
2336 if (ddr->ddr_sdram_cfg & 0x10000000 in check_fsl_memctl_config_regs()
2337 && ddr->ddr_sdram_cfg & 0x00008000) { in check_fsl_memctl_config_regs()
2349 fsl_ddr_cfg_regs_t *ddr, in compute_fsl_memctl_config_regs() argument
2397 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); in compute_fsl_memctl_config_regs()
2528 ddr->cs[i].bnds = (0 in compute_fsl_memctl_config_regs()
2534 ddr->cs[i].bnds = 0xffffffff; in compute_fsl_memctl_config_regs()
2537 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); in compute_fsl_memctl_config_regs()
2538 set_csn_config(dimm_number, i, ddr, popts, dimm_params); in compute_fsl_memctl_config_regs()
2539 set_csn_config_2(i, ddr); in compute_fsl_memctl_config_regs()
2549 set_ddr_eor(ddr, popts); in compute_fsl_memctl_config_regs()
2552 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); in compute_fsl_memctl_config_regs()
2555 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, in compute_fsl_memctl_config_regs()
2557 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2558 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2561 set_ddr_cdr1(ddr, popts); in compute_fsl_memctl_config_regs()
2562 set_ddr_cdr2(ddr, popts); in compute_fsl_memctl_config_regs()
2563 set_ddr_sdram_cfg(ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2569 ddr->debug[18] = popts->cswl_override; in compute_fsl_memctl_config_regs()
2571 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); in compute_fsl_memctl_config_regs()
2572 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2574 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2576 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2577 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2579 set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2581 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2582 set_ddr_data_init(ddr); in compute_fsl_memctl_config_regs()
2583 set_ddr_sdram_clk_cntl(ddr, popts); in compute_fsl_memctl_config_regs()
2584 set_ddr_init_addr(ddr); in compute_fsl_memctl_config_regs()
2585 set_ddr_init_ext_addr(ddr); in compute_fsl_memctl_config_regs()
2586 set_timing_cfg_4(ddr, popts); in compute_fsl_memctl_config_regs()
2587 set_timing_cfg_5(ddr, cas_latency); in compute_fsl_memctl_config_regs()
2589 set_ddr_sdram_cfg_3(ddr, popts); in compute_fsl_memctl_config_regs()
2590 set_timing_cfg_6(ddr); in compute_fsl_memctl_config_regs()
2591 set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2592 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2593 set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2594 set_ddr_dq_mapping(ddr, dimm_params); in compute_fsl_memctl_config_regs()
2597 set_ddr_zq_cntl(ddr, zq_en); in compute_fsl_memctl_config_regs()
2598 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); in compute_fsl_memctl_config_regs()
2600 set_ddr_sr_cntr(ddr, sr_it); in compute_fsl_memctl_config_regs()
2604 ddr->debug[2] = 0x00000400; in compute_fsl_memctl_config_regs()
2605 ddr->debug[4] = 0xff800800; in compute_fsl_memctl_config_regs()
2606 ddr->debug[5] = 0x08000800; in compute_fsl_memctl_config_regs()
2607 ddr->debug[6] = 0x08000800; in compute_fsl_memctl_config_regs()
2608 ddr->debug[7] = 0x08000800; in compute_fsl_memctl_config_regs()
2609 ddr->debug[8] = 0x08000800; in compute_fsl_memctl_config_regs()
2613 ddr->debug[2] |= 0x00000200; /* set bit 22 */ in compute_fsl_memctl_config_regs()
2621 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) || in compute_fsl_memctl_config_regs()
2622 IS_DBI(ddr->ddr_sdram_cfg_3)) { in compute_fsl_memctl_config_regs()
2623 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2624 ddr->debug[28] |= (0x9 << 20); in compute_fsl_memctl_config_regs()
2631 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2632 ddr->debug[28] &= 0xff0fff00; in compute_fsl_memctl_config_regs()
2634 ddr->debug[28] |= 0x0080006a; in compute_fsl_memctl_config_regs()
2636 ddr->debug[28] |= 0x0070006f; in compute_fsl_memctl_config_regs()
2638 ddr->debug[28] |= 0x00700076; in compute_fsl_memctl_config_regs()
2640 ddr->debug[28] |= 0x0060007b; in compute_fsl_memctl_config_regs()
2642 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) | in compute_fsl_memctl_config_regs()
2646 return check_fsl_memctl_config_regs(ddr); in compute_fsl_memctl_config_regs()
2658 struct ccsr_ddr __iomem *ddr = in erratum_a009942_check_cpo() local
2661 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; in erratum_a009942_check_cpo()
2666 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in erratum_a009942_check_cpo()
2679 cpo = ddr_in32(&ddr->debug[i]); in erratum_a009942_check_cpo()
2691 cpo = ddr_in32(&ddr->debug[13]); in erratum_a009942_check_cpo()
2699 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; in erratum_a009942_check_cpo()