Lines Matching refs:debug
72 debug("Workaround for ERRATUM_DDR111_DDR134\n"); in fsl_ddr_set_memctl_regs()
84 debug("Found cs%d_bns (0x%08x) covering 0xff000000, " in fsl_ddr_set_memctl_regs()
171 if (regs->debug[i]) { in fsl_ddr_set_memctl_regs()
172 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); in fsl_ddr_set_memctl_regs()
173 out_be32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
178 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
179 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
201 debug("Workaround for ERRATUM_DDR_A003\n"); in fsl_ddr_set_memctl_regs()
204 out_be32(&ddr->debug[2], 0x00000400); in fsl_ddr_set_memctl_regs()
209 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
210 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
211 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
212 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
217 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
329 out_be32(&ddr->debug[2], 0x0); in fsl_ddr_set_memctl_regs()
333 out_be32(&ddr->debug[12], save1); in fsl_ddr_set_memctl_regs()
334 out_be32(&ddr->debug[21], save2); in fsl_ddr_set_memctl_regs()
345 debug("Workaround for ERRATUM_DDR_115\n"); in fsl_ddr_set_memctl_regs()
349 setbits_be32(&ddr->debug[0], 1); in fsl_ddr_set_memctl_regs()
353 debug("Workaround for ERRATUM_DDR111_DDR134\n"); in fsl_ddr_set_memctl_regs()
361 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); in fsl_ddr_set_memctl_regs()
365 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", in fsl_ddr_set_memctl_regs()
369 setbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
370 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
428 debug("total %d GB\n", total_gb_size_per_controller); in fsl_ddr_set_memctl_regs()
429 debug("Need to wait up to %d * 10ms\n", timeout); in fsl_ddr_set_memctl_regs()
445 clrbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
446 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
451 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", in fsl_ddr_set_memctl_regs()
455 setbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
456 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
460 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", in fsl_ddr_set_memctl_regs()
464 out_be32(&ddr->debug[5], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
465 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); in fsl_ddr_set_memctl_regs()
468 out_be32(&ddr->debug[6], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
469 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); in fsl_ddr_set_memctl_regs()
472 setbits_be32(&ddr->debug[1], 0x800); in fsl_ddr_set_memctl_regs()
473 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
476 while (in_be32(&ddr->debug[1]) & 0x800) in fsl_ddr_set_memctl_regs()
480 clrbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
481 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
486 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
490 setbits_be32(&ddr->debug[1], 0x400); in fsl_ddr_set_memctl_regs()
491 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
494 while (in_be32(&ddr->debug[1]) & 0x400) in fsl_ddr_set_memctl_regs()
498 debug("Wait for %d * 10ms\n", timeout_save); in fsl_ddr_set_memctl_regs()
504 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
508 debug("Need to wait up to %d * 10ms\n", timeout); in fsl_ddr_set_memctl_regs()
520 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); in fsl_ddr_set_memctl_regs()
525 debug("Change cs%d_bnds back to 0x%08x\n", in fsl_ddr_set_memctl_regs()