34 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
35 			out_be32(&ddr->cs0_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
38 			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
39 			out_be32(&ddr->cs1_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
42 			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
43 			out_be32(&ddr->cs2_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
46 			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
47 			out_be32(&ddr->cs3_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
51 	out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);  in fsl_ddr_set_memctl_regs()
52 	out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);  in fsl_ddr_set_memctl_regs()
53 	out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);  in fsl_ddr_set_memctl_regs()
54 	out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);  in fsl_ddr_set_memctl_regs()
55 	out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);  in fsl_ddr_set_memctl_regs()
56 	out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);  in fsl_ddr_set_memctl_regs()
57 	out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);  in fsl_ddr_set_memctl_regs()
58 	out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);  in fsl_ddr_set_memctl_regs()
59 	out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);  in fsl_ddr_set_memctl_regs()
60 	out_be32(&ddr->sdram_data_init, regs->ddr_data_init);  in fsl_ddr_set_memctl_regs()
61 	out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);  in fsl_ddr_set_memctl_regs()
62 	out_be32(&ddr->init_addr, regs->ddr_init_addr);  in fsl_ddr_set_memctl_regs()
63 	out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);  in fsl_ddr_set_memctl_regs()
74 	out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);  in fsl_ddr_set_memctl_regs()