67 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_read_semaphore()  local
76 	tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_read_semaphore()
110 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_enable()  local
144 				&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);  in mxs_dma_enable()
147 			&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_enable()
154 			&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);  in mxs_dma_enable()
156 			&apbh_regs->ch[channel].hw_apbh_ch_sema);  in mxs_dma_enable()
158 			&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_enable()
182 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_disable()  local
196 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_disable()
211 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_reset()  local
215 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_reset()
218 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);  in mxs_dma_reset()
238 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_enable_irq()  local
248 			&apbh_regs->hw_apbh_ctrl1_set);  in mxs_dma_enable_irq()
251 			&apbh_regs->hw_apbh_ctrl1_clr);  in mxs_dma_enable_irq()
264 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_ack_irq()  local
272 	writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);  in mxs_dma_ack_irq()
273 	writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);  in mxs_dma_ack_irq()
501 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_wait_complete()  local
509 	if (mxs_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,  in mxs_dma_wait_complete()
554 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_circ_start()  local
562 		&apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);  in mxs_dma_circ_start()
563 	writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);  in mxs_dma_circ_start()
565 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_circ_start()
573 	struct mxs_apbh_regs *apbh_regs =  in mxs_dma_init()  local
576 	mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);  in mxs_dma_init()
580 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_init()
583 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_init()
588 		&apbh_regs->hw_apbh_ctrl0_set);  in mxs_dma_init()
591 		&apbh_regs->hw_apbh_ctrl0_clr);  in mxs_dma_init()