56 	uint    mixctrl;	/* For USDHC */  member
441 	esdhc_write32(&regs->mixctrl,  in esdhc_send_cmd_common()
442 	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)  in esdhc_send_cmd_common()
696 	u32 mixctrl;  in esdhc_set_timing()  local
698 	mixctrl = readl(&regs->mixctrl);  in esdhc_set_timing()
699 	mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);  in esdhc_set_timing()
714 		writel(mixctrl, &regs->mixctrl);  in esdhc_set_timing()
718 		mixctrl |= MIX_CTRL_DDREN;  in esdhc_set_timing()
719 		writel(mixctrl, &regs->mixctrl);  in esdhc_set_timing()
802 	u32 val, mixctrl;  in fsl_esdhc_execute_tuning()  local
811 		mixctrl = readl(&regs->mixctrl);  in fsl_esdhc_execute_tuning()
813 		mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);  in fsl_esdhc_execute_tuning()
816 		mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;  in fsl_esdhc_execute_tuning()
819 		writel(mixctrl, &regs->mixctrl);  in fsl_esdhc_execute_tuning()
823 	mixctrl = readl(&regs->mixctrl);  in fsl_esdhc_execute_tuning()
824 	mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);  in fsl_esdhc_execute_tuning()
825 	writel(mixctrl, &regs->mixctrl);  in fsl_esdhc_execute_tuning()
847 		val = readl(&regs->mixctrl);  in fsl_esdhc_execute_tuning()
849 		writel(val, &regs->mixctrl);  in fsl_esdhc_execute_tuning()
959 	esdhc_write32(&regs->mixctrl, 0x0);  in esdhc_init_common()
1103 	esdhc_write32(&regs->mixctrl, 0);  in fsl_esdhc_init()