159 	fsl_lbc_t *lbc = ctrl->regs;  in set_addr()  local
165 		out_be32(&lbc->fbar, page_addr >> 6);  in set_addr()
166 		out_be32(&lbc->fpar,  in set_addr()
171 		out_be32(&lbc->fbar, page_addr >> 5);  in set_addr()
172 		out_be32(&lbc->fpar,  in set_addr()
199 	fsl_lbc_t *lbc = ctrl->regs;  in fsl_elbc_run_command()  local
205 	out_be32(&lbc->fmr, priv->fmr | 3);  in fsl_elbc_run_command()
207 		out_be32(&lbc->mdr, ctrl->mdr);  in fsl_elbc_run_command()
210 	     in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));  in fsl_elbc_run_command()
213 	     in_be32(&lbc->fbar), in_be32(&lbc->fpar),  in fsl_elbc_run_command()
214 	     in_be32(&lbc->fbcr), priv->bank);  in fsl_elbc_run_command()
217 	out_be32(&lbc->lsor, priv->bank);  in fsl_elbc_run_command()
224 		ltesr = in_be32(&lbc->ltesr);  in fsl_elbc_run_command()
230 	out_be32(&lbc->ltesr, ctrl->status);  in fsl_elbc_run_command()
231 	out_be32(&lbc->lteatr, 0);  in fsl_elbc_run_command()
235 		ctrl->mdr = in_be32(&lbc->mdr);  in fsl_elbc_run_command()
240 	     ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));  in fsl_elbc_run_command()
250 	fsl_lbc_t *lbc = ctrl->regs;  in fsl_elbc_do_read()  local
253 		out_be32(&lbc->fir,  in fsl_elbc_do_read()
260 		out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |  in fsl_elbc_do_read()
263 		out_be32(&lbc->fir,  in fsl_elbc_do_read()
270 			out_be32(&lbc->fcr,  in fsl_elbc_do_read()
273 			out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);  in fsl_elbc_do_read()
284 	fsl_lbc_t *lbc = ctrl->regs;  in fsl_elbc_cmdfunc()  local
303 		out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */  in fsl_elbc_cmdfunc()
318 		out_be32(&lbc->fbcr, mtd->oobsize - column);  in fsl_elbc_cmdfunc()
333 		out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |  in fsl_elbc_cmdfunc()
336 		out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
341 		out_be32(&lbc->fbcr, 256);  in fsl_elbc_cmdfunc()
360 		out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
365 		out_be32(&lbc->fcr,  in fsl_elbc_cmdfunc()
369 		out_be32(&lbc->fbcr, 0);  in fsl_elbc_cmdfunc()
389 			out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
399 			out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
421 		out_be32(&lbc->fcr, fcr);  in fsl_elbc_cmdfunc()
437 			out_be32(&lbc->fbcr, ctrl->index);  in fsl_elbc_cmdfunc()
439 			out_be32(&lbc->fbcr, 0);  in fsl_elbc_cmdfunc()
449 		out_be32(&lbc->fir,  in fsl_elbc_cmdfunc()
452 		out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
453 		out_be32(&lbc->fbcr, 1);  in fsl_elbc_cmdfunc()
468 		out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);  in fsl_elbc_cmdfunc()
469 		out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);  in fsl_elbc_cmdfunc()
570 	fsl_lbc_t *lbc = ctrl->regs;  in fsl_elbc_wait()  local
577 	out_be32(&lbc->fir,  in fsl_elbc_wait()
580 	out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);  in fsl_elbc_wait()
581 	out_be32(&lbc->fbcr, 1);  in fsl_elbc_wait()