Lines Matching full:info
113 #define nand_writel(info, off, val) \ argument
114 writel((val), (info)->mmio_base + (off))
116 #define nand_readl(info, off) \ argument
117 readl((info)->mmio_base + (off))
318 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_timing() local
333 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_timing()
334 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_timing()
335 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_timing()
336 nand_writel(info, NDTR1CS0, ndtr1); in pxa3xx_nand_set_timing()
342 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_set_sdr_timing() local
372 info->ndtr0cs0 = ndtr0; in pxa3xx_nand_set_sdr_timing()
373 info->ndtr1cs0 = ndtr1; in pxa3xx_nand_set_sdr_timing()
374 nand_writel(info, NDTR0CS0, ndtr0); in pxa3xx_nand_set_sdr_timing()
375 nand_writel(info, NDTR1CS0, ndtr1); in pxa3xx_nand_set_sdr_timing()
382 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_init_timings() local
403 dev_err(&info->pdev->dev, "Error: timings not found\n"); in pxa3xx_nand_init_timings()
410 info->reg_ndcr |= NDCR_DWIDTH_M; in pxa3xx_nand_init_timings()
414 info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; in pxa3xx_nand_init_timings()
435 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info, in pxa3xx_set_datasize() argument
438 int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; in pxa3xx_set_datasize()
440 info->data_size = mtd->writesize; in pxa3xx_set_datasize()
444 info->oob_size = info->spare_size; in pxa3xx_set_datasize()
445 if (!info->use_ecc) in pxa3xx_set_datasize()
446 info->oob_size += info->ecc_size; in pxa3xx_set_datasize()
455 static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) in pxa3xx_nand_start() argument
459 ndcr = info->reg_ndcr; in pxa3xx_nand_start()
461 if (info->use_ecc) { in pxa3xx_nand_start()
463 if (info->ecc_bch) in pxa3xx_nand_start()
464 nand_writel(info, NDECCCTRL, 0x1); in pxa3xx_nand_start()
467 if (info->ecc_bch) in pxa3xx_nand_start()
468 nand_writel(info, NDECCCTRL, 0x0); in pxa3xx_nand_start()
473 if (info->use_spare) in pxa3xx_nand_start()
481 nand_writel(info, NDCR, 0); in pxa3xx_nand_start()
482 nand_writel(info, NDSR, NDSR_MASK); in pxa3xx_nand_start()
483 nand_writel(info, NDCR, ndcr); in pxa3xx_nand_start()
486 static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) in disable_int() argument
490 ndcr = nand_readl(info, NDCR); in disable_int()
491 nand_writel(info, NDCR, ndcr | int_mask); in disable_int()
494 static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) in drain_fifo() argument
496 if (info->ecc_bch) { in drain_fifo()
508 readsl(info->mmio_base + NDDB, data, 8); in drain_fifo()
511 while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { in drain_fifo()
513 dev_err(&info->pdev->dev, in drain_fifo()
524 readsl(info->mmio_base + NDDB, data, len); in drain_fifo()
527 static void handle_data_pio(struct pxa3xx_nand_info *info) in handle_data_pio() argument
529 unsigned int do_bytes = min(info->data_size, info->chunk_size); in handle_data_pio()
531 switch (info->state) { in handle_data_pio()
533 writesl(info->mmio_base + NDDB, in handle_data_pio()
534 info->data_buff + info->data_buff_pos, in handle_data_pio()
537 if (info->oob_size > 0) in handle_data_pio()
538 writesl(info->mmio_base + NDDB, in handle_data_pio()
539 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
540 DIV_ROUND_UP(info->oob_size, 4)); in handle_data_pio()
543 drain_fifo(info, in handle_data_pio()
544 info->data_buff + info->data_buff_pos, in handle_data_pio()
547 if (info->oob_size > 0) in handle_data_pio()
548 drain_fifo(info, in handle_data_pio()
549 info->oob_buff + info->oob_buff_pos, in handle_data_pio()
550 DIV_ROUND_UP(info->oob_size, 4)); in handle_data_pio()
553 dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, in handle_data_pio()
554 info->state); in handle_data_pio()
559 info->data_buff_pos += do_bytes; in handle_data_pio()
560 info->oob_buff_pos += info->oob_size; in handle_data_pio()
561 info->data_size -= do_bytes; in handle_data_pio()
564 static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info) in pxa3xx_nand_irq_thread() argument
566 handle_data_pio(info); in pxa3xx_nand_irq_thread()
568 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq_thread()
569 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); in pxa3xx_nand_irq_thread()
572 static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info) in pxa3xx_nand_irq() argument
578 if (info->cs == 0) { in pxa3xx_nand_irq()
586 status = nand_readl(info, NDSR); in pxa3xx_nand_irq()
589 info->retcode = ERR_UNCORERR; in pxa3xx_nand_irq()
591 info->retcode = ERR_CORERR; in pxa3xx_nand_irq()
592 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 && in pxa3xx_nand_irq()
593 info->ecc_bch) in pxa3xx_nand_irq()
594 info->ecc_err_cnt = NDSR_ERR_CNT(status); in pxa3xx_nand_irq()
596 info->ecc_err_cnt = 1; in pxa3xx_nand_irq()
603 info->max_bitflips = max_t(unsigned int, in pxa3xx_nand_irq()
604 info->max_bitflips, in pxa3xx_nand_irq()
605 info->ecc_err_cnt); in pxa3xx_nand_irq()
608 info->state = (status & NDSR_RDDREQ) ? in pxa3xx_nand_irq()
611 pxa3xx_nand_irq_thread(info); in pxa3xx_nand_irq()
615 info->state = STATE_CMD_DONE; in pxa3xx_nand_irq()
619 info->state = STATE_READY; in pxa3xx_nand_irq()
624 nand_writel(info, NDSR, NDSR_WRCMDREQ); in pxa3xx_nand_irq()
626 info->state = STATE_CMD_HANDLE; in pxa3xx_nand_irq()
636 nand_writel(info, NDCB0, info->ndcb0); in pxa3xx_nand_irq()
637 nand_writel(info, NDCB0, info->ndcb1); in pxa3xx_nand_irq()
638 nand_writel(info, NDCB0, info->ndcb2); in pxa3xx_nand_irq()
641 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_irq()
642 nand_writel(info, NDCB0, info->ndcb3); in pxa3xx_nand_irq()
646 nand_writel(info, NDSR, status); in pxa3xx_nand_irq()
648 info->cmd_complete = 1; in pxa3xx_nand_irq()
650 info->dev_ready = 1; in pxa3xx_nand_irq()
663 static void set_command_address(struct pxa3xx_nand_info *info, in set_command_address() argument
668 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) in set_command_address()
671 info->ndcb2 = 0; in set_command_address()
673 info->ndcb1 = ((page_addr & 0xFFFF) << 16) in set_command_address()
677 info->ndcb2 = (page_addr & 0xFF0000) >> 16; in set_command_address()
679 info->ndcb2 = 0; in set_command_address()
683 static void prepare_start_command(struct pxa3xx_nand_info *info, int command) in prepare_start_command() argument
685 struct pxa3xx_nand_host *host = info->host[info->cs]; in prepare_start_command()
689 info->buf_start = 0; in prepare_start_command()
690 info->buf_count = 0; in prepare_start_command()
691 info->oob_size = 0; in prepare_start_command()
692 info->data_buff_pos = 0; in prepare_start_command()
693 info->oob_buff_pos = 0; in prepare_start_command()
694 info->use_ecc = 0; in prepare_start_command()
695 info->use_spare = 1; in prepare_start_command()
696 info->retcode = ERR_NONE; in prepare_start_command()
697 info->ecc_err_cnt = 0; in prepare_start_command()
698 info->ndcb3 = 0; in prepare_start_command()
699 info->need_wait = 0; in prepare_start_command()
704 info->use_ecc = 1; in prepare_start_command()
706 pxa3xx_set_datasize(info, mtd); in prepare_start_command()
709 info->use_spare = 0; in prepare_start_command()
712 info->ndcb1 = 0; in prepare_start_command()
713 info->ndcb2 = 0; in prepare_start_command()
724 info->buf_count = mtd->writesize + mtd->oobsize; in prepare_start_command()
725 memset(info->data_buff, 0xFF, info->buf_count); in prepare_start_command()
729 static int prepare_set_command(struct pxa3xx_nand_info *info, int command, in prepare_set_command() argument
736 host = info->host[info->cs]; in prepare_set_command()
741 if (info->cs != 0) in prepare_set_command()
742 info->ndcb0 = NDCB0_CSEL; in prepare_set_command()
744 info->ndcb0 = 0; in prepare_set_command()
755 info->buf_start = column; in prepare_set_command()
756 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
761 info->buf_start += mtd->writesize; in prepare_set_command()
769 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); in prepare_set_command()
771 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) in prepare_set_command()
774 info->ndcb3 = info->chunk_size + in prepare_set_command()
775 info->oob_size; in prepare_set_command()
778 set_command_address(info, mtd->writesize, column, page_addr); in prepare_set_command()
783 info->buf_start = column; in prepare_set_command()
784 set_command_address(info, mtd->writesize, 0, page_addr); in prepare_set_command()
791 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
796 info->data_size = 0; in prepare_set_command()
802 if (is_buf_blank(info->data_buff, in prepare_set_command()
815 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
818 info->ndcb3 = info->chunk_size + in prepare_set_command()
819 info->oob_size; in prepare_set_command()
825 if (info->data_size == 0) { in prepare_set_command()
826 info->ndcb0 = NDCB0_CMD_TYPE(0x1) in prepare_set_command()
829 info->ndcb1 = 0; in prepare_set_command()
830 info->ndcb2 = 0; in prepare_set_command()
831 info->ndcb3 = 0; in prepare_set_command()
834 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) in prepare_set_command()
845 info->buf_count = 256; in prepare_set_command()
846 info->ndcb0 |= NDCB0_CMD_TYPE(0) in prepare_set_command()
850 info->ndcb1 = (column & 0xFF); in prepare_set_command()
851 info->ndcb3 = 256; in prepare_set_command()
852 info->data_size = 256; in prepare_set_command()
856 info->buf_count = host->read_id_bytes; in prepare_set_command()
857 info->ndcb0 |= NDCB0_CMD_TYPE(3) in prepare_set_command()
860 info->ndcb1 = (column & 0xFF); in prepare_set_command()
862 info->data_size = 8; in prepare_set_command()
865 info->buf_count = 1; in prepare_set_command()
866 info->ndcb0 |= NDCB0_CMD_TYPE(4) in prepare_set_command()
870 info->data_size = 8; in prepare_set_command()
874 info->ndcb0 |= NDCB0_CMD_TYPE(2) in prepare_set_command()
880 info->ndcb1 = page_addr; in prepare_set_command()
881 info->ndcb2 = 0; in prepare_set_command()
885 info->ndcb0 |= NDCB0_CMD_TYPE(5) in prepare_set_command()
896 dev_err(&info->pdev->dev, "non-supported command %x\n", in prepare_set_command()
909 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc() local
917 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc()
925 if (info->cs != host->cs) { in nand_cmdfunc()
926 info->cs = host->cs; in nand_cmdfunc()
927 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc()
928 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc()
931 prepare_start_command(info, command); in nand_cmdfunc()
933 info->state = STATE_PREPARED; in nand_cmdfunc()
934 exec_cmd = prepare_set_command(info, command, 0, column, page_addr); in nand_cmdfunc()
939 info->cmd_complete = 0; in nand_cmdfunc()
940 info->dev_ready = 0; in nand_cmdfunc()
941 info->need_wait = 1; in nand_cmdfunc()
942 pxa3xx_nand_start(info); in nand_cmdfunc()
948 status = nand_readl(info, NDSR); in nand_cmdfunc()
950 pxa3xx_nand_irq(info); in nand_cmdfunc()
952 if (info->cmd_complete) in nand_cmdfunc()
956 dev_err(&info->pdev->dev, "Wait timeout!!!\n"); in nand_cmdfunc()
961 info->state = STATE_IDLE; in nand_cmdfunc()
970 struct pxa3xx_nand_info *info = host->info_data; in nand_cmdfunc_extended() local
978 if (info->reg_ndcr & NDCR_DWIDTH_M) in nand_cmdfunc_extended()
986 if (info->cs != host->cs) { in nand_cmdfunc_extended()
987 info->cs = host->cs; in nand_cmdfunc_extended()
988 nand_writel(info, NDTR0CS0, info->ndtr0cs0); in nand_cmdfunc_extended()
989 nand_writel(info, NDTR1CS0, info->ndtr1cs0); in nand_cmdfunc_extended()
1009 prepare_start_command(info, command); in nand_cmdfunc_extended()
1019 info->need_wait = 1; in nand_cmdfunc_extended()
1020 info->dev_ready = 0; in nand_cmdfunc_extended()
1025 info->state = STATE_PREPARED; in nand_cmdfunc_extended()
1026 exec_cmd = prepare_set_command(info, command, ext_cmd_type, in nand_cmdfunc_extended()
1029 info->need_wait = 0; in nand_cmdfunc_extended()
1030 info->dev_ready = 1; in nand_cmdfunc_extended()
1034 info->cmd_complete = 0; in nand_cmdfunc_extended()
1035 pxa3xx_nand_start(info); in nand_cmdfunc_extended()
1041 status = nand_readl(info, NDSR); in nand_cmdfunc_extended()
1043 pxa3xx_nand_irq(info); in nand_cmdfunc_extended()
1045 if (info->cmd_complete) in nand_cmdfunc_extended()
1049 dev_err(&info->pdev->dev, "Wait timeout!!!\n"); in nand_cmdfunc_extended()
1055 if (info->data_size == 0 && command != NAND_CMD_PAGEPROG) in nand_cmdfunc_extended()
1062 if (info->data_size == 0 && in nand_cmdfunc_extended()
1069 if (info->data_size == info->chunk_size) in nand_cmdfunc_extended()
1079 info->data_size == 0) { in nand_cmdfunc_extended()
1084 info->state = STATE_IDLE; in nand_cmdfunc_extended()
1102 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_page_hwecc() local
1107 if (info->retcode == ERR_CORERR && info->use_ecc) { in pxa3xx_nand_read_page_hwecc()
1108 mtd->ecc_stats.corrected += info->ecc_err_cnt; in pxa3xx_nand_read_page_hwecc()
1110 } else if (info->retcode == ERR_UNCORERR) { in pxa3xx_nand_read_page_hwecc()
1117 info->retcode = ERR_NONE; in pxa3xx_nand_read_page_hwecc()
1122 return info->max_bitflips; in pxa3xx_nand_read_page_hwecc()
1129 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_byte() local
1132 if (info->buf_start < info->buf_count) in pxa3xx_nand_read_byte()
1134 retval = info->data_buff[info->buf_start++]; in pxa3xx_nand_read_byte()
1143 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_word() local
1146 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { in pxa3xx_nand_read_word()
1147 retval = *((u16 *)(info->data_buff+info->buf_start)); in pxa3xx_nand_read_word()
1148 info->buf_start += 2; in pxa3xx_nand_read_word()
1157 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_read_buf() local
1158 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_read_buf()
1160 memcpy(buf, info->data_buff + info->buf_start, real_len); in pxa3xx_nand_read_buf()
1161 info->buf_start += real_len; in pxa3xx_nand_read_buf()
1169 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_write_buf() local
1170 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); in pxa3xx_nand_write_buf()
1172 memcpy(info->data_buff + info->buf_start, buf, real_len); in pxa3xx_nand_write_buf()
1173 info->buf_start += real_len; in pxa3xx_nand_write_buf()
1185 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_waitfunc() local
1187 if (info->need_wait) { in pxa3xx_nand_waitfunc()
1190 info->need_wait = 0; in pxa3xx_nand_waitfunc()
1196 status = nand_readl(info, NDSR); in pxa3xx_nand_waitfunc()
1198 pxa3xx_nand_irq(info); in pxa3xx_nand_waitfunc()
1200 if (info->dev_ready) in pxa3xx_nand_waitfunc()
1204 dev_err(&info->pdev->dev, "Ready timeout!!!\n"); in pxa3xx_nand_waitfunc()
1212 if (info->retcode == ERR_NONE) in pxa3xx_nand_waitfunc()
1221 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info) in pxa3xx_nand_config_flash() argument
1223 struct pxa3xx_nand_host *host = info->host[info->cs]; in pxa3xx_nand_config_flash()
1227 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; in pxa3xx_nand_config_flash()
1228 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0; in pxa3xx_nand_config_flash()
1229 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0; in pxa3xx_nand_config_flash()
1234 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) in pxa3xx_nand_detect_config() argument
1240 struct pxa3xx_nand_host *host = info->host[0]; in pxa3xx_nand_detect_config()
1241 uint32_t ndcr = nand_readl(info, NDCR); in pxa3xx_nand_detect_config()
1245 info->chunk_size = 2048; in pxa3xx_nand_detect_config()
1248 info->chunk_size = 512; in pxa3xx_nand_detect_config()
1253 info->reg_ndcr = ndcr & ~NDCR_INT_MASK; in pxa3xx_nand_detect_config()
1254 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); in pxa3xx_nand_detect_config()
1255 info->ndtr1cs0 = nand_readl(info, NDTR1CS0); in pxa3xx_nand_detect_config()
1259 static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) in pxa3xx_nand_init_buff() argument
1261 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in pxa3xx_nand_init_buff()
1262 if (info->data_buff == NULL) in pxa3xx_nand_init_buff()
1269 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_sensing() local
1270 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_sensing()
1276 mtd = info->host[info->cs]->mtd; in pxa3xx_nand_sensing()
1280 info->reg_ndcr = 0x0; /* enable all interrupts */ in pxa3xx_nand_sensing()
1281 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; in pxa3xx_nand_sensing()
1282 info->reg_ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); in pxa3xx_nand_sensing()
1283 info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */ in pxa3xx_nand_sensing()
1300 static int pxa_ecc_init(struct pxa3xx_nand_info *info, in pxa_ecc_init() argument
1305 info->chunk_size = 2048; in pxa_ecc_init()
1306 info->spare_size = 40; in pxa_ecc_init()
1307 info->ecc_size = 24; in pxa_ecc_init()
1313 info->chunk_size = 512; in pxa_ecc_init()
1314 info->spare_size = 8; in pxa_ecc_init()
1315 info->ecc_size = 8; in pxa_ecc_init()
1325 info->ecc_bch = 1; in pxa_ecc_init()
1326 info->chunk_size = 2048; in pxa_ecc_init()
1327 info->spare_size = 32; in pxa_ecc_init()
1328 info->ecc_size = 32; in pxa_ecc_init()
1330 ecc->size = info->chunk_size; in pxa_ecc_init()
1335 info->ecc_bch = 1; in pxa_ecc_init()
1336 info->chunk_size = 2048; in pxa_ecc_init()
1337 info->spare_size = 32; in pxa_ecc_init()
1338 info->ecc_size = 32; in pxa_ecc_init()
1340 ecc->size = info->chunk_size; in pxa_ecc_init()
1349 info->ecc_bch = 1; in pxa_ecc_init()
1350 info->chunk_size = 1024; in pxa_ecc_init()
1351 info->spare_size = 0; in pxa_ecc_init()
1352 info->ecc_size = 32; in pxa_ecc_init()
1354 ecc->size = info->chunk_size; in pxa_ecc_init()
1358 dev_err(&info->pdev->dev, in pxa_ecc_init()
1371 struct pxa3xx_nand_info *info = host->info_data; in pxa3xx_nand_scan() local
1372 struct pxa3xx_nand_platform_data *pdata = info->pdata; in pxa3xx_nand_scan()
1376 if (pdata->keep_config && !pxa3xx_nand_detect_config(info)) in pxa3xx_nand_scan()
1380 info->chunk_size = 512; in pxa3xx_nand_scan()
1384 dev_info(&info->pdev->dev, "There is no chip on cs %d!\n", in pxa3xx_nand_scan()
1385 info->cs); in pxa3xx_nand_scan()
1392 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) in pxa3xx_nand_scan()
1393 nand_writel(info, NDECCCTRL, 0x0); in pxa3xx_nand_scan()
1401 dev_err(&info->pdev->dev, in pxa3xx_nand_scan()
1407 ret = pxa3xx_nand_config_flash(info); in pxa3xx_nand_scan()
1427 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) { in pxa3xx_nand_scan()
1430 dev_err(&info->pdev->dev, in pxa3xx_nand_scan()
1450 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, in pxa3xx_nand_scan()
1462 kfree(info->data_buff); in pxa3xx_nand_scan()
1465 info->buf_size = mtd->writesize + mtd->oobsize; in pxa3xx_nand_scan()
1466 ret = pxa3xx_nand_init_buff(info); in pxa3xx_nand_scan()
1469 info->oob_buff = info->data_buff + mtd->writesize; in pxa3xx_nand_scan()
1478 static int alloc_nand_resource(struct pxa3xx_nand_info *info) in alloc_nand_resource() argument
1486 pdata = info->pdata; in alloc_nand_resource()
1490 info->variant = pxa3xx_nand_get_variant(); in alloc_nand_resource()
1493 ((u8 *)&info[1] + sizeof(*host) * cs); in alloc_nand_resource()
1496 info->host[cs] = host; in alloc_nand_resource()
1499 host->info_data = info; in alloc_nand_resource()
1506 chip->controller = &info->controller; in alloc_nand_resource()
1518 info->buf_size = INIT_BUFFER_SIZE; in alloc_nand_resource()
1519 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); in alloc_nand_resource()
1520 if (info->data_buff == NULL) { in alloc_nand_resource()
1526 disable_int(info, NDSR_MASK); in alloc_nand_resource()
1530 kfree(info->data_buff); in alloc_nand_resource()
1535 static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info) in pxa3xx_nand_probe_dt() argument
1557 info->mmio_base = in pxa3xx_nand_probe_dt()
1586 info->pdata = pdata; in pxa3xx_nand_probe_dt()
1596 static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info) in pxa3xx_nand_probe() argument
1601 ret = pxa3xx_nand_probe_dt(info); in pxa3xx_nand_probe()
1605 pdata = info->pdata; in pxa3xx_nand_probe()
1607 ret = alloc_nand_resource(info); in pxa3xx_nand_probe()
1615 struct mtd_info *mtd = info->host[cs]->mtd; in pxa3xx_nand_probe()
1623 info->cs = cs; in pxa3xx_nand_probe()
1648 struct pxa3xx_nand_info *info; in board_nand_init() local
1652 info = kzalloc(sizeof(*info) + in board_nand_init()
1655 if (!info) in board_nand_init()
1658 ret = pxa3xx_nand_probe(info); in board_nand_init()