62 		control = readl(GMAC0_DMA_TX_CTRL_ADDR);  in dma_ctrlflags()
64 		if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) {  in dma_ctrlflags()
81 	uint32_t v = readl(reg);  in reg32_clear_bits()
88 	uint32_t v = readl(reg);  in reg32_set_bits()
102 	       readl(GMAC0_DMA_TX_CTRL_ADDR),  in dma_tx_dump()
103 	       readl(GMAC0_DMA_TX_PTR_ADDR),  in dma_tx_dump()
104 	       readl(GMAC0_DMA_TX_ADDR_LOW_ADDR),  in dma_tx_dump()
105 	       readl(GMAC0_DMA_TX_ADDR_HIGH_ADDR),  in dma_tx_dump()
106 	       readl(GMAC0_DMA_TX_STATUS0_ADDR),  in dma_tx_dump()
107 	       readl(GMAC0_DMA_TX_STATUS1_ADDR));  in dma_tx_dump()
134 	       readl(GMAC0_DMA_RX_CTRL_ADDR),  in dma_rx_dump()
135 	       readl(GMAC0_DMA_RX_PTR_ADDR),  in dma_rx_dump()
136 	       readl(GMAC0_DMA_RX_ADDR_LOW_ADDR),  in dma_rx_dump()
137 	       readl(GMAC0_DMA_RX_ADDR_HIGH_ADDR),  in dma_rx_dump()
138 	       readl(GMAC0_DMA_RX_STATUS0_ADDR),  in dma_rx_dump()
139 	       readl(GMAC0_DMA_RX_STATUS1_ADDR));  in dma_rx_dump()
274 	      (readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK)  in dma_init()
277 	      (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK)  in dma_init()
379 	intstatus = readl(GMAC0_INT_STATUS_ADDR);  in gmac_check_tx_done()
417 	stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR) & D64_RS0_CD_MASK;  in gmac_check_rx_done()
418 	stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR) & D64_RS0_CD_MASK;  in gmac_check_rx_done()
445 	stat0 = readl(GMAC0_DMA_RX_STATUS0_ADDR);  in gmac_check_rx_done()
446 	stat1 = readl(GMAC0_DMA_RX_STATUS1_ADDR);  in gmac_check_rx_done()
454 	control = readl(GMAC0_DMA_RX_CTRL_ADDR);  in gmac_check_rx_done()
489 		SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &  in gmac_disable_dma()
500 		SPINWAIT(((status = (readl(GMAC0_DMA_TX_STATUS0_ADDR) &  in gmac_disable_dma()
514 		SPINWAIT(((status = (readl(GMAC0_DMA_RX_STATUS0_ADDR) &  in gmac_disable_dma()
539 		control = readl(GMAC0_DMA_TX_CTRL_ADDR);  in gmac_enable_dma()
554 		control = (readl(GMAC0_DMA_RX_CTRL_ADDR) &  in gmac_enable_dma()
571 		control |= readl(GMAC0_DMA_RX_CTRL_ADDR) & D64_RC_BL_MASK;  in gmac_enable_dma()
594 		tmp = readl(GMAC_MII_CTRL_ADDR);  in gmac_mii_busywait()
628 	value = readl(GMAC_MII_DATA_ADDR) & 0xffff;  in gmac_miiphy_read()
685 	cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);  in gmac_enable_local()
748 	cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);  in gmac_set_speed()
786 	tmp = readl(AMAC0_IO_CTRL_DIRECT_ADDR);  in gmac_mac_init()
803 	cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);  in gmac_mac_init()
830 	tmp = readl(SWITCH_GLOBAL_CONFIG_ADDR);  in gmac_mac_init()
838 	tmp = readl(CRMU_CHIP_IO_PAD_CONTROL_ADDR);  in gmac_mac_init()
843 	tmp = readl(GMAC_MII_CTRL_ADDR);  in gmac_mac_init()
866 	cmdcfg = readl(UNIMAC0_CMD_CFG_ADDR);  in gmac_mac_init()