Lines Matching refs:dma_p
140 struct eth_dma_regs *dma_p = priv->dma_regs_p; in tx_descs_init() local
174 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); in tx_descs_init()
180 struct eth_dma_regs *dma_p = priv->dma_regs_p; in rx_descs_init() local
214 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); in rx_descs_init()
266 struct eth_dma_regs *dma_p = priv->dma_regs_p; in _dw_eth_halt() local
269 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); in _dw_eth_halt()
277 struct eth_dma_regs *dma_p = priv->dma_regs_p; in designware_eth_init() local
281 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); in designware_eth_init()
293 while (readl(&dma_p->busmode) & DMAMAC_SRST) { in designware_eth_init()
311 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); in designware_eth_init()
314 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, in designware_eth_init()
315 &dma_p->opmode); in designware_eth_init()
317 writel(readl(&dma_p->opmode) | FLUSHTXFIFO, in designware_eth_init()
318 &dma_p->opmode); in designware_eth_init()
321 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); in designware_eth_init()
324 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); in designware_eth_init()
358 struct eth_dma_regs *dma_p = priv->dma_regs_p; in _dw_eth_send() local
414 writel(POLL_DATA, &dma_p->txpolldemand); in _dw_eth_send()